LG GD910, Руководство по обслуживанию

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8. CIRCUIT DIAGRAM
LGE Internal Use Only Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
PWR
URXD
UTXD
3G 2.5G
GND
RX
TX
VCHAR
ON_SW
VBAT
C
2
D
E
Large Block Memory
A
1
ADD 0.4Pitch Mark
G
B
2V62_VIO Domain
3 6 4 8 9 11
TPs for MP
H
(2048Mbit NAND / 1024 Mbit DDR SDRAM, 1.8V I/O)
TOUCH
F
C
9
CHARGE PUMP
5 3 11
VGA CAMERA
G
MAIN PMIC
10
E
6
A
4
I2C1 I2C2
2
B
5
10
D
12
H
8
(1%)
1
UART
12
F
7
BASE BAND PROCESSOR
7
1u
C122
R113
10K
4.7K R115
VSS8
AA18 M14
VSS9
P22
WAIT_N
H21
WR_N
R6
VSS20 VSS21
U6
VSS22
W6 E5
VSS23 VSS24
A4
VSS25
AA4
VSS26
F3 H3
VSS27 VSS28
K2
VSS29
N2 V23
VSS3
AA1
VSS30
VSS4
AA22
VSS5
B21 T21
VSS6 VSS7
F19
VMICP
G5
VREFN
H6
H5
VREFP
D23
VSS0 VSS1
K23
VSS10
A13
VSS11
K12 L12
VSS12
M12
VSS13 VSS14
N12 P12
VSS15 VSS16
A11 V10
VSS17
B8
VSS18 VSS19
AC7
VSS2
N23 P23
VDD_FUSE_FS
B3
VDD_HIGH_OUT
VDD_MAIN0
K13
VDD_MAIN1
L13 M13
VDD_MAIN2
N13
VDD_MAIN3
P13
VDD_MAIN4 VDD_MAIN5
K11 L11
VDD_MAIN6
M11
VDD_MAIN7 VDD_MAIN8
N11
VDD_MAIN9
P11
VDD_PLL0
G9
VDD_PLL1
A10
VDD_RTC
E7
G6
VMICN
VDDP_LOW2
AB1 AC13
VDDP_LOW3
VDDP_LOW4_1
R23
VDDP_LOW4_2
H23 E23
VDDP_MEM_ETM0 VDDP_MEM_ETM1
M23
VDDP_MEM_ETM2
E19
VDDP_MEM_ETM3
M19
VDDP_MEM_ETM4
E17 E13
VDDP_MEM_ETM5
V11
VDDP_MMC
VDDP_SIM
P3
VDDVB
K1
VDDVBR1
D1
VDDVBR2
G3
VDD_E_FUSE
B11 AC14
VDD4 VDDA
AC22
VDDBB
K6
VDDBG
F6 E6
VDDD
A21
VDDLS1 VDDLS2
A14
VDDM
A9
VDDP_DIGA
V1 W14
VDDP_DIGB
VDDP_DIGC1
AB10
VDDP_DIGC2
AB4
VDDP_DIGD
W17 V19
VDDP_DIGE
VDDP_HIGH2
AB6 A5
VDDP_LOW1
U18
USIF1_CTS_N USIF1_RTS_N
Y22
USIF1_RXD_MRST
M18 Y23
USIF1_TXD_MTSR
L7
USIF2_CTS_N
N3
USIF2_RTS_N USIF2_RXD_MRST
T1
K7
USIF2_TXD_MTSR USIF3_RXD_MRST
AA23
USIF3_SCLK
V18 U19
USIF3_TXD_MTSR USIF_RXD
AC6
USIF_TXD
AC3
VDD1
A17 A8
VDD2 VDD3
AC9
TRIG_IN
W5
TRST_N
V8
W8
T_IN0
T_IN1
AA8
V6
T_OUT0
AB8
T_OUT1
AA11
T_OUT10
P7
T_OUT2
T_OUT3
W11
T_OUT4
U10
U9
T_OUT5
T_OUT6
AA10
T_OUT7
W10
N7
T_OUT8
T_OUT9
W9
UMTS_WKP
U1
SPCU_RQ_IN2
T2
SWIF_TXRX
P6
TCK
AB5
TDI
Y2
TDO
AB3
AA6
TMS
G10
TRACECLK
B14
TRACEPKT0
C12
TRACEPKT1
TRACEPKT2
E11
E12
TRACEPKT3
E14
TRACEPKT4
F10
TRACEPKT5
C11
TRACEPKT6
TRACEPKT7
B10
E16
TRACESYNC
PM_INT
F8
RAS_N
B15
T22
RD_N
RESET_N
E8
RF_CLK
AA5
V9
RF_DATA
RF_STR0
AB2
AC4
RF_STR1
RSTOUT_N
R2
B7
RST_N
RTCK
V7
RTC_OUT
F7
SDCLKO
G19
SPCU_RC_OUT0
T5
P2
SPCU_RQ_IN0
R1
SPCU_RQ_IN1
MMCI1_CLK
AB13
R7
MMCI1_CMD
MMCI1_DAT0
T6
MMCI1_DAT1
P10
MMCI1_DAT2
V5
MMCI1_DAT3
W12
MMCI2_CLK
L17
AB21
MMCI2_CMD
AA20
MMCI2_DAT0
MON1
AC2
AA12
MON2
E10
OSC32K
N6
PAOUT1
PIPESTAT0
C14
F12
PIPESTAT1
G11
PIPESTAT2
AC1
LINE_RIGHT_NC3
E3
M0
M1
D2
C6
M10
D3
M2
M3
C1
M4
C2
C4
M5
M6
B4
C5
M7
B5
M8
B6
M9
L1
MICN1 MICN2
L3
K3
MICP1
L2
MICP2
AB9
JTAG_TRST_N
AC8
JTSG_TMS
KP_IN0
V21
KP_IN1
N18 U21
KP_IN2
P17
KP_IN3 KP_IN4
R17 U23
KP_IN5 KP_IN6
U22
KP_OUT0
N17
W21
KP_OUT1 KP_OUT2
V22 R18
KP_OUT3
A23
LINE_LEFT_NC0
A1
LINE_LEFT_NC1
AC23
LINE_RIGHT_NC2
W2
I2S1_CLK1
V2
I2S1_RX
W1
I2S1_TX I2S1_WA0
Y1
R5
I2S2_CLK0
J7
I2S2_CLK1
U2
I2S2_RX I2S2_TX
V3
I2S2_WA0
U3
T3
I2S2_WA1
W23
IRDA_RX IRDA_TX
W22
K5
IREF
AC10
JTAG_RTCK
AA2
JTAG_TDI
AC5
JTAG_TDO
GPIO3
B22
C22
GPIO4
A19
GPIO5
GPIO6
B20
C20
GPIO7
GPIO8
A18
GPIO9
A20
GUARD
F5
I2C1_SCL
AB7 AA7
I2C1_SDA
W3
I2C2_SCL I2C2_SDA
U5
I2RF_DATA
B2
A2
I2RF_SCLK
A3
I2RF_STR0
W7
I2S1_CLK0
E9
F32K
FCDP_RBN
F9
FWP
B9
C23
GPIO0
B23
GPIO1
C7
GPIO10
GPIO11
B19
GPIO12
A16
B17
GPIO13
B18
GPIO14
A15
GPIO15
GPIO16
B13
C13
GPIO17
GPIO18
A12
GPIO19
B12
GPIO2
A22
J1
EPN1_2 EPP1_1
H2 H1
EPP1_2 EPPA1_1
G2 G1
EPPA1_2 EPPA2_1
E2 E1
EPPA2_2
F2
EPREF1
F1
EPREF2
AC11
ESIF_ADVN
F23
ESIF_CLK
ESIF_CSN
AC12
AB11
ESIF_RDN
G23
ESIF_WAITN
ESIF_WRN
AB12
F11
F26M_1
U14
DIF_D3
R13
DIF_D4 DIF_D5
W16
DIF_D6
V16
DIF_D7
AA16 AA19
DIF_D8 DIF_HD
W19
AA17
DIF_RD
R12
DIF_RESET1 DIF_RESET2
R11
DIF_VD
Y21
DIF_WR
W18
N14
DSPIN0 DSPIN1
T23 T18
DSPOUT1 EPN1_1
J2
C10
CLKOUT0
CLKOUT2
W15
CS0_N
L19
K22
CS1_N
K21
CS2_N
L18
CS3_N
CSA0_N
H19
CSA1_N
G21
CSA2_N
H18
G18
CSA3_N
DIF_CD
V17
DIF_CS1
AB20
DIF_CS2
P14 U13
DIF_D0
AB16
DIF_D1 DIF_D2
U15
L10
CIF_D0 CIF_D1
AA13 AB14
CIF_D2
M10
CIF_D3 CIF_D4
AB15
V15
CIF_D5 CIF_D6
AA14
CIF_D7
N10
W13
CIF_HSYNC
V13
CIF_PCLK
V12
CIF_PD CIF_RESET
V14
CIF_VSYNC
U11
G13
CKE
CLK26M
C8
B1
CLK32K
L5
BB_I
L6
BB_IX
M5
BB_Q
M6
BB_QX
BC0_N
E22
BC1_N
F21
F15
BC2_N
D21
BC3_N
F22
BFCLKO1
BFCLKO2
E21
BOOT_CFG0
A7
BOOT_CFG1
A6
E15
CAS_N
CC_CLK
P1
N5
CC_IO
P5
CC_RST
AC21
ARXN_I
ARXN_Q
AB22
ARXP_I
AC20
AB23
ARXP_Q
AC18
ATXN_I
ATXN_Q
AC19
ATXP_I
AB18
ATXP_Q
AB19
ATX_PA_ADC
AB17
ATX_PA_DAC
AC15
AC16
ATX_VGA_DAC
J5
AUXGND AUXN1
M2 N1
AUXN2 AUXP1
M1
AUXP2
M3
AD12
L21
AD13
J22
N22
AD14
AD15
J23
T19
AD2
P18
AD3
AD4
M21
AD5
M22
AD6
L23
L22
AD7
AD8
L14
AD9
R19
ADV_N
P21
AFC
Y3
J6
AGND
AC17
AIREF
A22
K18
A23
F16
J17
A24
A25
F18
J18
A26
J13
A3
A4
F17
C19
A5
J11
A6
A7
G14
C18
A8
C17
A9
N21
AD0
AD1
N19
AD10
R22
P19
AD11
G15
A0
A1
D22
A10
E18
K10
A11
B16
A12
C16
A13
A14
F14
F13
A15
A16
K19
A17
K17
H22
A18
J19
A19
J12
A2
A20
K14
G22
A21
PMB8879
U102
0.1u
C132
_RAS
F3
_RE
D6
_WED
M3
_WEN
N3
_WP
VDD1
C8
VDD2
P6
VDD3
P4
VDDQ1
P8
VDDQ2
C5
VSS1
C9
VSS2
G2
VSS3
H10
VSS4
P7
VSS5
VSS6
P9
P5
VSSQ
E6
_CAS
G3
_CE
C6
_CLK
_CS
D5
F6
Q10
NC63
Q11
NC64
Q12
NC65
T1
NC66
T2
NC67
T3
T10
NC68 NC69
T11
B1
NC7
NC70
T12
B2
NC8
B3
NC9
E3
R__B
K7
UDQM
L7
UDQS
H2
VCCN1
C4
NC48 NC49
K9
A11
NC5
K10
NC50
L2
NC51 NC52
M2
NC53
N2
NC54
P1 P2
NC55
P3
NC56 NC57
P11 P12
NC58
Q1
NC59
A12
NC6
Q2
NC60 NC61
Q3
NC62
NC33 NC34
H9 J2
NC35
NC36
J3
NC37
J4 J5
NC38 NC39
J6
NC4
A10
NC40
J7
NC41
J8 J9
NC42
J10
NC43
J11
NC44
K2
NC45
K4
NC46
K5
NC47
K8
NC19
A2
NC2
D3
NC20 NC21
E2
NC22
H11 F2
NC23 NC24
F9
NC25
G6
NC26
G9
NC27
G10
NC28
H3
NC29
H4 A3
NC3
NC30
H5 H6
NC31
H7
NC32
H8
I_O6
I_O7
C10
I_O8
N11
I_O9
M11
K6
LDQM
LDQS
L6
NC1
A1 B10
NC10
B11
NC11 NC12
B12
NC13
C1
NC14
C2 C3
NC15 NC16
C11
NC17
C12 D1
NC18
D2
M6
N6
DQ7
DQ8
M7
DQ9
N7
P10
I_O0
N10
I_O1
L11
I_O10
I_O11
K11
I_O12
G11
I_O13
F11
E11
I_O14
D11
I_O15
M10
I_O2
L10
I_O3
F10
I_O4
E10
I_O5
D10
F5
CKE
D7
K3
CLE
CLK
C7
DQ0
L4
DQ1
M4
DQ10
L8
M8
DQ11
N8
DQ12
L9
DQ13
M9
DQ14
N9
DQ15
DQ2
N4
DQ3
L5
M5
DQ4
DQ5
N5
DQ6
D4
A1
E4
A10
G5
A11
F7
A12
E7
A13
E9
A2
F4
A3
G4
A4
G8
A5
F8
A6
E8
D8
A7
A8
D9
A9
G7
L3
ALE
BA0
E5
BA1
2V5_VAUDB
U100
H8BCS0SI0MAP_56M
A0
3
Q
8
VCC
_CLR
2
1
_PR
_Q
5
NC7SZ74L8X
U101
CK
7
6
D
GND
4
0.1u
C121
2V9_SIM
SD_DATA(0)
R117
0.1u
2.2K
C116 C117
0.1u
C109
_RD
2V62_VIO
10n
100K
R114
C107
0.1u
_NAND_CS
2V62_VIO
C108
2V11_RTC
USB_VBUS
0.1u
0.1u
VBAT
1V8_SD
C135
0.1u
C123
C130
10n
3.3K
R106
0.1u
C105
1K
R107
C115
0.1u
C133
0.1u
0.1u
C111
VBAT
C127
10n
3.3K
R105 10
R103
TP_MON_TxD
0.1u
2V5_VAUDA
1V8_SD
C114
100K
1u
R101
C129
10n
C106
1V8_SD
10n
C102
VCHG
22p
C139
C112
0.1u
1V8_SD
C118
0.1u
1V8_SD
R108
1K
TP107
TP_MULTI_PORT_1
C136
220n
0.1u
C140
100nH
L101
R118 2.2K
C100
0.1u
2V11_RTC
10K
R102
R116 4.7K
5
ON_SW
11
RTS
RX
2
3
TX
6
VBAT
UART1
CTS
12
DSR
10
GND
1
NC1
4
7
NC2
NC3
8
9
NC4
22K R104
1V8_SD
_WR
TP_GND
1 2
TP106
390K
R100
32.768KHz
X100
2V8_VMME
BA1
0.1u
C120
0.1u
2V62_VIO
C131
C101
TP_DSR
VBAT
1u
TP_USB_VBUS
C125
1u
1V35_CORE
C134
2V5_VAUDB
0.1u
2V62_VIO
2V62_VIO
1u
C104
0.1u
C124
2V62_VIO
2V62_VIO
TP_VBAT
1V35_VPLL
1
2
3
4
5
6
CN102
C126
0.1u
0.1u
C103
0.1u
C113
0.1u
TP_MON_RxD
C145
0.1u
C119
NC7WZ08L8X
U103
7
A1
3
A2
6
B1
2
B2
4
GND
8
VCC
1
Y1
Y2
5
TP_MULTI_PORT_0
22p
1V35_CORE
C138
C110
0.1u
C137
0.1u
1u
TP_RPWRON
C128
1V35_VPLL
22K
R112
C141
0.1u
L100
100nH
BATTERY
10K
R110
USB_EN
TP_BATTERY
MULTI_PORT_0
RPWRON
DSR
KEY_IN(2)
KEY_OUT(1)
PM_VCXO_EN
WDCDC_VCON
MON_TxD
MON_RxD
RPWRON
UART_TX
UART_RX
DSR
NAND_IO(11)
NAND_IO(10)
NAND_IO(1)
NAND_IO(0)
SD_DATA(9)
SD_DATA(8)
SD_DATA(7)
SD_DATA(6)
SD_DATA(5)
SD_DATA(4)
SD_DATA(3)
SD_ADD(10)
SD_ADD(9)
SD_ADD(8)
SD_ADD(7)
SD_ADD(6)
SD_ADD(5)
SD_ADD(4)
SD_DATA(2)
SD_ADD(3)
SD_ADD(2)
SD_ADD(1)
SD_ADD(0)
SD_DATA(15)
SD_DATA(14)
SD_DATA(13)
SD_DATA(12)
SD_DATA(11)
SD_DATA(10)
SD_DATA(1)
SD_DATA(0)
3G_TX_QP
3G_TX_IP
3G_TX_QN
3G_TX_IN
3G_RX_QP
3G_RX_IP
3G_RX_QN
3G_RX_IN
BA1
NAND_IO(9)
NAND_IO(8)
NAND_IO(7)
NAND_IO(6)
NAND_IO(5)
NAND_IO(4)
NAND_IO(3)
NAND_IO(2)
NAND_IO(15)
NAND_IO(14)
NAND_IO(13)
NAND_IO(12)
VGA_CAM_DATA[2] VGA_CAM_DATA[1] VGA_CAM_DATA[0]
SIM_RST
SIM_IO
SIM_CLK
_CAS
SDCLKI
UDQS
LDQS
_BC1
_BC0
2G_QN
2G_QP
2G_IN
2G_IP
3G_VGC_TX
SD_ADD(12)
SD_ADD(11)
_CS3
_RAM_CS
_NAND_CS
CAM_MCK
CLK32K
CKE
CAM_VSYNC
VGA_RESET
_CHG_EN
CAM_PCK
CAM_HSYNC
VGA_CAM_DATA[7] VGA_CAM_DATA[6] VGA_CAM_DATA[5] VGA_CAM_DATA[4] VGA_CAM_DATA[3]
_DIF_RESET
_DIF_RD
CAM_IO_OFF
DIF_D7 DIF_D6 DIF_D5 DIF_D4 DIF_D3 DIF_D2 DIF_D1 DIF_D0
_DIF_CS1
LCD_RS
BA0
SD_ADD(13)
3G_MASTERON
_WP
FCDP
26MHZ
_WR
_WAIT
_RD
_CS3
BFCLKO
BA1
SPK_OUT_P SPK_OUT_N
WDOG
BT_WAKEUP
CLK32K
_DIF_WR
DIF_VSYNC
A_RESET
BT_PCM_SYNC
BT_PCM_OUT
BT_PCM_IN
BT_PCM_CLK
3G_EN
3G_CLK
3G_DATA
I2C2_SDA
I2C2_SCL
I2C1_SDA
I2C1_SCL
3G_LD
ANT_SEL6
ANT_SEL5
ANT_SEL4
3G_PA_MODE1
RF_TEMP
KEY_OUT(3)
KP_OUT(0)
KP_IN(6)
TA_DETECT
KEY_IN(1)
BACK_UP_EN
USB_OEn
TOUCH_ATT
BT_HOST_WAKEUP
BT_RESET_N
SPK_AMP_EN
_CHG_EOC
ANT_SEL1
TXON_PA
I2C2_SCL_TOUCH
SDCLKO
RTC_OUT
A_RESET
_PPR
2G_EN
2G_DATA
2G_CLK
_RESET
_RD
_RAS
PM_INT
PA_LEVEL
MON_RxD
UART_BT_TX
VIB_EN
UART_BT_RX
RPWRON
BT_REG_ON
UART_BT_RTS UART_BT_CTS
UART_TX
UART_RX
USB_DAT_VP USB_SE0_VM
I2C2_SDA_TOUCH
ANT_SEL3
ANT_SEL2
PA_MODE
BFCLKO
_WR
_WAIT
VMIC_P
RESOURCE_CTRL
MON_TxD
USB_DP
USB_DM
MULTI_PORT_1
MIC_N MIC_P
EXTRSTn
PMRSTn
PM_INT SPOWER_INT
_RESET
_CAS
_NAND_CS
SDCLKI
_RAM_CS
_RAS
_RD
_WR
_WR
_WP
FCDP
_BC1
UDQS
PM_VCXO_EN
SD_ADD(0)
BA0
BA1
CKE
SD_ADD(1)
SDCLKO
_BC0
LDQS
NAND_IO(8)
NAND_IO(9)
NAND_IO(10)
NAND_IO(11)
NAND_IO(12)
NAND_IO(13)
NAND_IO(14)
NAND_IO(15)
AFC
SD_DATA(9)
SD_DATA(10)
SD_DATA(11)
SD_DATA(12)
SD_DATA(13)
SD_DATA(14)
SD_DATA(15)
NAND_IO(0:15)
NAND_IO(0)
NAND_IO(1)
NAND_IO(2)
NAND_IO(3)
NAND_IO(4)
NAND_IO(5)
NAND_IO(6)
NAND_IO(7)
SD_ADD(11)
SD_ADD(12)
SD_ADD(13)
SD_ADD(0)
SD_ADD(1)
SD_DATA(0:15)
SD_DATA(0)
SD_DATA(1)
SD_DATA(2)
SD_DATA(3)
SD_DATA(4)
SD_DATA(5)
SD_DATA(6)
SD_DATA(7)
SD_DATA(8)
SD_DATA(0:15)
SD_ADD(0:10)
NAND_IO(0:15)
SD_ADD(0:13)
SD_ADD(2)
SD_ADD(3)
SD_ADD(4)
SD_ADD(5)
SD_ADD(6)
SD_ADD(7)
SD_ADD(8)
SD_ADD(9)
SD_ADD(10)