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LGE Internal Use Only
Copyright © 2010 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL BRIEF
3.8.2 VGA Camera Interface
3. Technical Brief
Figure. Schematic of VGA Camera Module and I/F
The VGA Camera module is mounted to SPK FPCB. Its interface is dedicated camera interface port in
MSM7227. The camera port supply 24MHz master clock to camera module and receive 19.2MHz pixel
clock (max.30fps@VGA), vertical sync signal, horizontal sync signal, reset signal and 8bits data from
camera module. The camera module is controlled by I2C port from MSM7227.
100p
C210
CN200
41
40
42
39
43
38
44
37
45
36
46
35
47
34
48
33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
65
16
66
15
67
14
68
13
69
12
70
11
71
10
72
9
73
8
74
7
75
6
76
5
77
4
78
3
79
2
80
1
100
R205
DNI
C204
7.5p
C203
1
R201
470
R211
7.5p
C214
4.7K
90
2
R
4.7K
01
2
R
470
R212
470
R213
R
W
P
V+
V8.
1_
D
CL
_
G
E
R
V
V5.
1_
B
G
R_
G
E
R
V
V6.
2_
B
G
R_
G
E
R
V
V8.
2_
D
CL
_
G
E
R
V
V0.
3_
C
M
M_
G
E
R
V
V0.
3_
R
OT
O
M_
G
E
R
V
470
R214
V6.
2_
P
M
S
M_
G
E
R
V
56K
51
2
R
56K
61
2
R
CAM_VDD_2.8V
VREG_MSMP_2.6V
V6.
2_
R
O
S
N
E
S_
G
E
R
V
RCV_P
RCV_N
VBACK_UP
MIC_BIAS
LCD_CVT_INT
LCD_CVT_RESET_N
TOUCH_I2C_SDA
TOUCH_I2C_SCL
KEY_ROW[0]
KEY_ROW[1]
KEY_COL[0]
KEY_COL[1]
MOTION_INT
LCD_SUBPM_RESET_N
LCD_SUBPM_I2C_SCL
LCD_SUBPM_I2C_SDA
MOTION_I2C_SCL
MOTION_I2C_SDA
PROXI_I2C_SCL
PROXI_I2C_SDA
PROXI_OUT
LIN_MOTOR_EN
LIN_MOTOR_PWM
MICROSD_CLK
MICROSD_CMD
SPK_P
SPK_N
MIC_SEL
MIC_P
MICROSD_DET_N
MICROSD_DATA[3]
MICROSD_DATA[2]
MICROSD_DATA[1]
MICROSD_DATA[0]
TOUCH_ACK
LCD_RESET_N
LCD_CVT_VSYNC
MDDI_P_DATA_P
MDDI_P_STB_P
LCD_MAKER_ID
MDDI_P_STB_M
MDDI_P_DATA_M
CAM_VSYNC
CAM_DATA[7]
CAM_DATA[6]
CAM_DATA[5]
CAM_DATA[4]
CAM_DATA[3]
CAM_DATA[2]
CAM_DATA[1]
CAM_DATA[0]
CAM_MCLK
VGA_CAM_PWDN
VGA_CAM_RESET_N
MCAM_RESET
CAM_I2C_SCL
CAM_I2C_SDA
CAM_DATA[8]
CAM_DATA[9]
MCAM_PWDN
PM_ON_SW
MIC_VGND
FLT_CAM_HSYNC
FLT_CAM_PCLK
MAIN & SUB I/F CONNECTOR
0.1u
C211
0.1u
C212
60
FB201
U200
1
F
E3
E4
E2
A5
C4
A4
D4
D6
C3
C5
C2
D3
C1
C6
B4
B5
B2
B1
B3
D2
E5
D1
B6
A3
A2
IOVDD
DCLK
DVDD
HSYNC
AVDD
VSYNC
DATA0
DATA1
DATA2
EXTCLK
DATA3
PWRDWN
DATA4
RESET
DATA5
SDA
DATA6
SCL
DATA7
GND1
GND2
VDD15_1
GND3
VDD15_2
GND4
D
N
G
P
0.1u
C209
CAM_VDD_2.8V
CAM_VDD_1.8V
D200
CAM_PCLK
CAM_VSYNC
CAM_HSYNC
CAM_MCLK
VGA_CAM_PWDN
VGA_CAM_RESET_N
CAM_I2C_SCL
CAM_I2C_SDA
S_VGA_CAM_DATA[0]
S_VGA_CAM_DATA[1]
S_VGA_CAM_DATA[2]
S_VGA_CAM_DATA[3]
S_VGA_CAM_DATA[4]
S_VGA_CAM_DATA[5]
S_VGA_CAM_DATA[6]
S_VGA_CAM_DATA[7]
SUB FPCB
12MHz
Содержание GD88O
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