LG GB108, Руководство по обслуживанию, Страница: 40 / 115

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3.15.1 FM Tuner (GB105a/b&GB106&GB107a/b&GB108 only)
The Si4702 patented digital low-IF architecture reduces external components and eliminates the
need for factory adjustments. The receive (RX) section integrates a low noise amplifier (LNA)
supporting the worldwide FM broadcast band (76 to 108 MHz). Anautomatic gain control (AGC)
circuit controls the gain of the LNA to optimize sensitivity and rejection of strong interferers.
For two-wire operation, a transfer begins with the START condition. The control word is latched
internally on rising SCLK edges and is eight bits in length, comprised of a seven bit device
address equal to 0010000b and a read/write bit (write = 0 and read = 1). The device
acknowledges the address by setting SDIO low on the next falling SCLK edge. For write
operations, the device acknowledge is followed by an eight bit data word latched internally on
rising edges of SCLK. The device always acknowledges the data by setting SDIO low on the next
falling SCLK edge. An internal address counter automatically increments to allow continuous data
byte writes, starting with the upper byte of register 02h, followed by the lower byte of register 02h,
and onward until the lower byte of the last register is reached. The internal address counter then
automatically wraps around to the upper byte of register 00h and proceeds from there until
continuous writes cease. Data transfer ceases with the STOP command. After every STOP
command, the internal address counter is reset. For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling SCLK edges. An internal address counter
automatically increments to allow continuous data byte reads, starting with the upper byte of
register 0Ah, followed by the lower byte of register 0Ah, and onward until the lower byte of the last
register is reached. The internal address counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until continuous reads cease. After each byte of
data is read, the controller IC should return an acknowledge if an additional byte of data will be
requested. Data transfer ceases with the STOP command. After every STOP command, the
internal address counter is reset.
3.15.2 Headphone Amplifier
The TS486 is a dual audio power amplifier capable of driving, in single-ended mode, either a 16
or a 32W stereo headset. Capable of descending to low voltages, it delivers up to 90mW per
channel (into 16W loads) of continuous average power with 0.3% THD+N in the audio bandwitdth
from a 5V power supply. An externally-controlled standby mode reduces the supply current to
10nA (typ.). The unity gain stable TS486 can be configured by external gain-setting resistors or
used in a fixed gain version.