LG 47LW6500, Руководство по обслуживанию

Страница: 88 / 117

-
88
-
H
ig
h
C
hassis
B
C
M
35230
(IC
101)
H
ig
h
C
hassis
High Ch
a
s
s
is
B
C
M
35230
B
C
M
35230
(IC1
0
(IC1
0
1 1
)
)
NVR
A
M
(1
M
, I
C
103
)
NVR
A
M
NVR
A
M
( (
1M
1M
, IC
1
0
, IC
1
0
3
3
) )
NA
N
D
F
L
A
S
H
(8Gb
it, IC102)
NA
N
D
F
L
A
S
H
NA
N
D
F
L
A
S
H
( (
8 8
G G
bit
bit
, IC10 , IC10
2 2
) )
NA
N
D
_
DA
T
A
[0
-7
]
EE
PRO
M_
SCL/
SD
A
LED
_
R/Buzz
K
E
Y1/2
,
IR
EE
PRO
M
(IC
601
)
EE
PRO
M
(IC
601
)
NEC_Mi
co
m
IC
602
NEC_Mi
co
m
NEC_Mi
co
m
IC
602
IC
602
IR & K
E
Y
P901
IR & K
E
Y
IR & K
E
Y
P901 P901
S
C
L2
/S
D
A
2_3.3
V
Po
w
e
r B/D
P502
Po
w
e
r B/D
Po
w
e
r B/D
P502 P502
INV
_CTL
,RL
_
O
N
Debu
gg
er
P601
Debu
gg
er
Debu
gg
er
P601 P601
NEC_
IS
P
_T
X
/R
X,
OCD
1
A
/B
,FL
MD0,MINC
OM_
R
ES
ET
SO
C_
Rese
t
N
A
ND _
WEb
/A
L
E/CL
E
…
LP
F
S
C
L1
/S
D
A
1_3.3
V
Spea
ke
r
P1
801
A
udi
o A
M
P
N
T
P
-7400L
IC
1802
A
udi
o A
M
P
A
udi
o A
M
P
NTP NTP
- -
7400L 7400L
IC
1802
IC
1802
A
U
D
_LRCH/LR
CK/SCK, A
M
P
_
Mute
SPK_L
+/-
SPK_R
+/-
PWM
S
D
A
/SC
L1_3
.3V
TX
A
/B
/C/D [
0
-4
]
N/P,
TX
A
/B
/C/D CLK
N/CLKP
LVDS
_
T
X
A
/B
[
0
-4] N/
P,
LVDS
_
T
X
A
/B
C
L
KN/CLKP
LVDS
_
T
XC/D
[
0
-4] N/
P,
LVDS
_
T
XC/D
C
L
KN/CLKP
FRC
M
S
T
7398Q
IC
4000
FRC FRC
M
S
T
7398Q
M
S
T
7398Q
IC
4000
IC
4000
FRC_RE
S
E
T
L
E
D_
B
/LG LOG
O
LED Dr
iv
in
g B/
D
P4300
(51P
IN
)
LED Dr
iv
in
g B/
D
LED Dr
iv
in
g B/
D
P4300
(51P
IN
)
P4300
(51P
IN
)
LED Dr
iv
in
g B/
D
P4301
(41P
IN
)
LED Dr
iv
in
g B/
D
LED Dr
iv
in
g B/
D
P4301
(41P
IN
)
P4301
(41P
IN
)
W
oofer
N
T
P
-7400L
IC
1801
W
oofer W
oofer
NTP
NTP
-
-
7400L 7400L
IC
1801
IC
1801
S
C
L1
/S
D
A
1_3.3
V
A
U
D
_LRCH/LR
CK/SCK, A
M
P
_
Mute
S
PK_Woof
er
+/
-
W
oofer
P1802
W
oofer
W
oofer
P1802
P1802
A
UD_
M
A
ST
ER_C
L
K
A
UD_
M
A
ST
ER_C
L
K
SP
I FL
A
S
H
( I
C
4002
,2
M
)
SP
I FL
A
S
H
( I
C
4002
,2
M
)
SP
I_
DO
/CS/
SCLK/DI
S/T_
SCL/SD
A
Ea
rp
h
one
A
M
P
IC
1804
Ea
rp
h
one
A
M
P
Ea
rp
h
one
A
M
P
IC
1804
IC
1804
H
P
_L
/R
_O
U
T
_
N
/P
HP_
L
/R
OUT
HP
DDR3
( I
C
4100
,4
M
)
DDR3
( I
C
4100
,4
M
)
FRC_
A
[0-
1
3
],FR
C_B
A
0
/1
/2,FRC
_
MCLK/CL
E
/MCLKB…
（
DDR3_
A
[0-
1
3]
,DDR3
_B
A
0
/1
/2,
DDR3
_MCLK…
）
FRC_D
Q
U/D
Q
L[0-
7]
(DDR3_D
QU
/D
Q
L
[0-
7
])
DDR
( I
C
401
,I
C
402
)
DDR
( I
C
401
,I
C
402
)
DDR_
A
A
…
，
DDR0
1/
2
3
_
CLK
/CL
Kb,……
DDR_D
Q
[0-
7
]/[
8
-1
5]/[
1
6
-2
3]/[
2
4
-3
1]
Block diagram for GP3 M/B_Output