THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR3_DQU[1]
DDR3_DQL[1]
DDR3_DQL[3]
DDR3_A[8]
DDR3_A[3]
DDR3_A[12]
DDR3_A[13]
DDR3_A[5]
DDR3_DQL[7]
DDR3_A[7]
DDR3_DQL[0]
DDR3_DQL[6]
DDR3_A[11]
DDR3_A[2]
DDR3_DQU[0]
DDR3_A[10]
DDR3_DQU[2]
DDR3_A[9]
DDR3_DQL[4]
DDR3_DQU[6]
DDR3_A[0]
DDR3_A[4]
DDR3_DQL[5]
DDR3_A[6]
DDR3_DQU[4]
DDR3_A[1]
DDR3_DQU[3]
DDR3_DQL[2]
DDR3_DQU[7]
DDR3_DQU[5]
FRC_DQL[4]
+1.5V_FRC_DDR
FRC_A[10]
FRC_DQSL
R5312
22
MVREFDQ
FRC_DQSUB
DDR3_DQSLB
DDR3_BA0
DDR3_DQSLB
DDR3_ODT
DDR3_A[10]
FRC_DQL[3]
R5310
56
R5316
22
FRC_DQL[5]
DDR3_CKE
FRC_CASB
FRC_DQU[3]
DDR3_DMU
FRC_DQU[6]
R5321
22
FRC_BA2
FRC_DQU[7]
FRC_CKE
C5312
0.1uF
AR5306
22
DDR3_DQL[6]
FRC_DQL[7]
FRC_DQL[6]
C5314
0.1uF
+1.5V_FRC_DDR
DDR3_MCK
+1.5V_FRC_DDR
DDR3_BA0
FRC_DQL[0]
DDR3_A[6]
DDR3_DQSUB
DDR3_A[2]
AR5304
22
DDR3_MCK
DDR3_DQL[0-7]
DDR3_DQSL
DDR3_DQU[2]
AR5302
22
DDR3_BA2
DDR3_DQL[0]
FRC_DML
DDR3_DML
DDR3_ODT
DDR3_A[8]
FRC_A[11]
FRC_A[9]
FRC_DQSLB
R5304
1K
1%
DDR3_BA1
DDR3_DQU[0-7]
DDR3_BA1
DDR3_A[9]
DDR3_DQL[4]
DDR3_WEB
DDR3_A[0-13]
FRC_ODT
DDR3_DML
R5302
1K
1%
FRC_BA1
R5301
1K
1%
DDR3_DQU[7]
MVREFDQ
C5313
0.1uF
DDR3_DQU[1]
DDR3_RASB
DDR3_DQL[5]
FRC_A[12]
DDR3_DQL[3]
DDR3_DQU[5]
+1.5V_FRC_DDR
AR5307
22
FRC_A[4]
R5320
22
FRC_A[13]
DDR3_A[1]
AR5305
22
DDR3_DMU
FRC_DQU[2]
FRC_DQU[0]
DDR3_RASB
DDR3_CASB
FRC_A[8]
DDR3_A[11]
+1.5V_FRC_DDR
DDR3_DQSUB
R5309
56
FRC_A[2]
C5305
0.1uF
DDR3_A[12]
DDR3_DQU[6]
DDR3_MCK
DDR3_DQU[0]
DDR3_CASB
FRC_MCLK
FRC_DQU[5]
DDR3_WEB
R5313
22
+1.5V_FRC_DDR
AR5309
22
FRC_A[5]
DDR3_A[0]
DDR3_DQU[3]
R5317
22
C5306
0.1uF
R5314
22
FRC_WEB
DDR3_MCKB
C5315
0.01uF
25V
C5308
0.1uF
R5311
22
AR5303
22
DDR3_MCKB
FRC_DQU[1]
DDR3_MCKB
DDR3_DQSU
C5309
0.1uF
FRC_A[7]
FRC_RASB
FRC_DMU
FRC_A[1]
MVREFCA
AR5301
22
C5304
22uF
10V
DDR3_DQL[7]
DDR3_A[3]
FRC_DQSU
DDR3_A[13]
C5302
0.1uF
C5310
0.1uF
FRC_BA0
DDR3_BA2
DDR3_CKE
MVREFCA
FRC_A[6]
R5318
22
C5303
0.1uF
16V
FRC_DQL[2]
AR5308
22
C5307
0.1uF
R5319
22
DDR3_DQU[4]
C5301
0.1uF
R5303
1K
1%
DDR3_DQL[1]
C5311
0.1uF
FRC_MCLKB
DDR3_A[5]
DDR3_DQL[2]
R5315
22
FRC_DQL[1]
DDR3_DQSU
DDR3_DQSL
FRC_A[0]
DDR3_A[7]
FRC_A[3]
DDR3_A[4]
R5307
150
OPT
FRC_DQU[4]
R5305
240
1%
H5TQ1G63DFR-PBC
IC5301
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
R5308
0
DDR3_RESETB
FRC_DDR3_RESETB
DDR3_RESETB
R5322
22
DDR3 4Mbit
53
MStar URSA5
55
2010. 08.18
Place Close to DDR Pin
Place Close to DDR Pin
Close to DDR Pin
Place the serail damping resistors
in the middle of DRAM pattern
DDR3 1.5V De-Cap Place near Memory
Содержание 47LW6500
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