LG 22LQ630H, Руководство по обслуживанию

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THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
MLB-201209-0120P-N2
L1227
3.3V_Proidiom
3.3V_Proidiom
FE_DEMOD_SCL
002:S15
3.3V_Proidiom
+3.3V_Normal
1uF
25V
C2179
OPT
FPGA_RESET
012:P17
3.3V_Proidiom
1uF
25V
C2255
MAX809RTR
IC1210
1
GND
3 VCC 2
RESET
MSDA_3.3V
0.1uF
16V
C2178
MLB-201209-0120P-N2
L1228
OPT
3.3V_Proidiom
MSCL_3.3V
1N4148W
D1250
OPT
FE_DEMOD_SDA
002:S15
DE_H_SYSCLK
012:P18
27MHz
X1006
6
1
2 5
3 4
0
R2446
0
R2448
47
K
R
23
96
47
K
R
23
95
22 R2387
100
R2564
4
.7
K
R
25
63
10K
R2390
OPT
XMARK_1.8V
0.1uF
16V
XMARK
C2260
22uF
16V
XMARK
C2261
GND
2
N-
P
0
2
1
0-
9
0
2
1
0
2-
B
L
M
K
R
A
M
X
1
5
2
1
L
0.1uF
16V
XMARK
C2262
22uF
16V
XMARK
C2263
3.3V_Proidiom
4.7uF TDK
C2271
3.3V_Proidiom
TS[4] 001:AL17
0
.1
u
F
16V
C
22
08
TS[5]
001:AL17
10K R1790
0
.0
1
u
F
C
21
91
3.3V_Proidiom
0
.1
u
F
16V
C
22
11
0
XMARK
R2586
M
L
B
-2
0
1
2
0
9
-0
1
2
0
P
-N
2
L
1
2
3
5
0
LGDT1129
R2587
GND
0
.1
u
F
16V
C
21
97
TS[3] 001:AL17
0
.0
1
u
F
25V
XMARK
C
22
65
10K
XMARK
R2570
M
L
B
-2
0
1
2
0
9
-0
1
2
0
P
-N
2
L
1
2
3
4
22 R2415
0
XMARK
R2571
M
L
B
-2
0
1
2
0
9
-0
1
2
0
P
-N
2
L
1
2
3
6
XMARK_1.8V
PM_TS_SYNC
001:AL20
0
XMARK
R2573
0
.1
u
F
16V
C
21
95
0
.1
u
F
16V
C
22
13
0
.1
u
F
16V
C
22
01
0
XMARK
R2575
GND
10K
OPT
R2406
0
.1
u
F
16V
C
22
00
XMARK_1.8V
0
XMARK
R2585
0
.1
u
F
16V
C
22
09
LGDT1129
IC1209
LGDT1129
H1
CLK1
B8
IO2_29/TP_SOP
B9
IO2_21/TP_VALID
B10
IO2_17/TP_ERR
C5
IO2_41/TP_DATA[7]
C6
IO2_36/TP_DATA[6]
C7
IO2_31/TP_DATA[5]
C8
IO2_25/TP_DATA[4]
C9
IO2_23/TP_DATA[3]
C10
IO2_18/TP_DATA[2]
C11
IO2_14/TP_DATA[1]
C12
IO2_8/TP_DATA[0]
M1
IO1_29
C3
IO1_2
C2
IO1_3
B1
IO1_4
G5
IO1_5
F4
IO1_6
D3
IO1_7
E4
IO1_8
F5
IO1_9
E3
IO1_10
D2
IO1_11
E2
IO1_12
G1
CLK0
B2
IO2_48/RESET
D14
IO3_37/I2C_SCK
E14
IO3_34/I2C_SDA
K4
DCLK
K13
CONF_DONE
H3
NCONFIG
J 4
NCE
H2
DATA0
G4
IO1_21SO
K3
IO1_22/ASDO
H4
NCEO
J13
NSTATUS
J 3
MSEL0
J 2
MSEL1
J14
TCK
H15
TDO
J15
TMS
H14
TDI
D4
IO1_1/INIT_DONE
D1
IO1_13
F3
IO1_14
G3
IO1_15
F2
IO1_16
E1
IO1_17
G2
IO1_18
F1
IO1_19
H5
IO1_20
J 1
IO1_23
K2
IO1_24
L3
IO1_25
K1
IO1_26
L1
IO1_27
L2
IO1_28
N1
IO1_30
M2
IO1_31
N2
IO1_32
M3
IO1_33
L5
IO1_34
M4
IO1_35
N
3
IO
1
_
3
6
K
5
IO
1
_
3
7
L
4
IO
1
_
3
8
R
1
IO
1
_
3
9
P
2
IO
1
_
4
0
P
3
IO
1
_
4
1
N
4
IO
1
_
4
2
R
2
IO
4
_
1
T
2
IO
4
_
2
R
3
IO
4
_
3
P
4
IO
4
_
4
R
4
IO
4
_
5
T
4
IO
4
_
6
R
5
IO
4
_
7
M
5
IO
4
_
9
M
6
IO
4
_
1
0
N
5
IO
4
_
1
1
N
6
IO
4
_
1
2
R
6
IO
4
_
1
4
M
7
IO
4
_
1
5
T
6
IO
4
_
1
6
R
7
IO
4
_
1
7
N
7
IO
4
_
1
9
T
8
IO
4
_
2
1
M
8
IO
4
_
2
2
N
8
IO
4
_
2
3
M
10
IO
4
_
2
5
T
9
IO
4
_
2
7
N
9
IO
4
_
2
9
T
11
IO
4
_
3
1
N
10
IO
4
_
3
2
N
11
IO
4
_
3
6
N
12
IO
4
_
3
7
M
9
IO
4
_
3
8
M
11
IO
4
_
3
9
M
12
IO
4
_
4
0
R
12
IO
4
_
4
2
T
13
IO
4
_
4
3
R
13
IO
4
_
4
4
R
14
IO
4
_
4
5
P
1
3
IO
4
_
4
6
T
15
IO
4
_
4
7
R
15
IO
4
_
4
8
N
13
IO
3
_
1
P
1
4
IO
3
_
2
P
1
5
IO
3
_
3
R
16
IO
3
_
4
N
15
IO
3
_
5
N
16
IO
3
_
6
K
12
IO
3
_
7
K
14
IO
3
_
8
L
12
IO
3
_
9
N
14
IO
3
_
1
0
M
13
IO
3
_
1
1
M
14
IO
3
_
1
2
L
13
IO
3
_
1
3
M
15
IO
3
_
1
4
M
16
IO
3
_
1
5
L
14
IO
3
_
1
6
L
15
IO
3
_
1
7
L
16
IO
3
_
1
8
K
16
IO
3
_
1
9
K
15
IO
3
_
2
0
J1
6
IO
3
_
2
1
H16
CLK3
G16
CLK2
H12
IO3_22
G14
IO3_23
G13
IO3_24
G15
IO3_25
F16
IO3_26
F14
IO3_27
F13
IO3_28
F15
IO3_29
E16
IO3_30
E15
IO3_31
D16
IO3_32
D15
IO3_33
F12
IO3_35
E13
IO3_36
H13
IO3_38
G12
IO3_39
B16
IO3_40
C15
IO3_41
C14
IO3_42
D13
IO3_43
B15
IO2_1
A15
IO2_2
B14
IO2_3
C13
IO2_4
B13
IO2_5
A13
IO2_6
B12
IO2_7
A2
IO2_47
E12
IO2_9
E11
IO2_10
E9
IO2_11
D12
IO2_12
D11
IO2_13
B3
IO2_46
B11
IO2_15
A11
IO2_16
D10
IO2_19
A9
IO2_20
D9
IO2_22
C4
IO2_45
E10
IO2_24
B4
IO2_44
D8
IO2_26
E8
IO2_27
A8
IO2_28
D7
IO2_30
A4
IO2_43
B7
IO2_32
A6
IO2_33
E7
IO2_34
P12
IO4_41/CH_DATA[7]
P11
IO4_35/CH_DATA[6]
P10
IO4_33/CH_DATA[5]
P9
IO4_28/CH-DATA[4]
P8
IO4_24/CH_DATA[3]
P7
IO4_18/CH_DATA[2]
P6
IO4_13/CH_DATA[1]
P5
IO4_8/CH_DATA[0]
R10
IO4_30/CH_ERR
R9
IO4_26/CH_SOP
R8
IO4_20/CH_VALID
R11
IO4_34/CH_CLK
A
7
V
C
C
IN
T
_1
A
10
V
C
C
IN
T
_2
G
8
V
C
C
IN
T
_3
G
10
V
C
C
IN
T
_4
H
7
V
C
C
IN
T
_5
H
9
V
C
C
IN
T
_6
J8
V
C
C
IN
T
_7
J1
0
V
C
C
IN
T
_8
K
7
V
C
C
IN
T
_9
K
9
V
C
C
IN
T
_1
0
T
7
V
C
C
IN
T
_1
1
T
10
V
C
C
IN
T
_1
2
C
1
V
C
C
IO
1_
1
G
6
V
C
C
IO
1_
2
P
1
V
C
C
IO
1_
3
T
3
V
C
C
IO
4_
1
L
7
V
C
C
IO
4_
2
L
10
V
C
C
IO
4_
3
T
14
V
C
C
IO
4_
4
P
1
6
V
C
C
IO
3_
1
K
11
V
C
C
IO
3_
2
C
16
V
C
C
IO
3_
3
A
14
V
C
C
IO
2_
1
F
1
0
V
C
C
IO
2_
2
F
7
V
C
C
IO
2_
3
A
3
V
C
C
IO
2_
4
A
1
G
N
D
_1
A
16
G
N
D
_2
A
5
G
N
D
_3
A
12
G
N
D
_4
F
6
G
N
D
_5
F
8
G
N
D
_6
F
9
G
N
D
_7
F
1
1
G
N
D
_8
G
7
G
N
D
_9
G
9
G
N
D
_1
0
G
11
G
N
D
_1
1
H
8
G
N
D
_1
2
H
10
G
N
D
_1
3
J7
G
N
D
_1
4
J9
G
N
D
_1
5
K
6
G
N
D
_1
6
K
8
G
N
D
_1
7
K
10
G
N
D
_1
8
L
6
G
N
D
_1
9
L
8
G
N
D
_2
0
L
9
G
N
D
_2
1
L
11
G
N
D
_2
2
T
1
G
N
D
_2
3
T
5
G
N
D
_2
4
T
12
G
N
D
_2
5
T
16
G
N
D
_2
6
J6
G
N
D
A
_P
L
L
1
J5
G
N
D
G
_P
L
L
1
J1
1
G
N
D
A
_P
L
L
2
J1
2
G
N
D
G
_P
L
L
2
H
6
V
C
C
A
_P
L
L
1
H
11
V
C
C
A
_P
L
L
2
B
6
IO
2
_
3
5
B
5
IO
2
_
4
2
D
6
IO
2
_
3
7
D
5
IO
2
_
3
8
E
6
IO
2
_
3
9
E
5
IO
2
_
4
0
22 R2417
FPGA_RESET 012:B19
4.7K
O
PT
R2418
0
.1
u
F
16V
C
22
15
0
.1
u
F
16V
C
21
99
0
XMARK
R2589
1
u
F
50V
C
21
85
XMARK_1.8V
TS_VALID
001:AL17
100 R2443
1
u
F
50V
C
21
92
10K R1789
M
L
B
-2
0
1
2
0
9
-0
1
2
0
P
-N
2
L
1
2
3
2
TS[7] 001:AL17
0
.1
u
F
16V
XMARK
C
22
64
0
.1
u
F
16V
C
22
16
0
.1
u
F
16V
C
22
14
0
XMARK
R2581
0
XMARK
R2572
BLM18PG121SN1D
XMARK
L1253
0
.0
1
u
F
C
21
88
TS[0] 001:AL17
TS_CLK 001:AL17
0
.1
u
F
16V
C
22
03
XMARK_1.8V
10K R1788
0
.1
u
F
16V
C
21
87
10K
R2422
0
.1
u
F
16V
C
22
02
0
.1
u
F
16V
C
22
17
0
.1
u
F
16V
C
22
18
BLM18PG121SN1D
XMARK
L1252
0
LGDT1129
R2582
MLB-201209-0120P-N2
L1231
BLM18PG121SN1D
XMARK
L1255
0
XMARK
R2583
0
.1
u
F
16V
C
22
05
1K
R2403
4.7uF
16V
C2186
0
.1
u
F
16V
C
21
94
0
.1
u
F
16V
C
22
04
TS[2]
001:AL17
0
.1
u
F
16V
C
22
06
3.3V_Proidiom
0
XMARK
R2588
0
XMARK
R2580
TS[6] 001:AL17
0
.1
u
F
16V
C
21
96
62pF
50V
C2219
OPT
10K R2409
LGDT1129
3.3V_Proidiom
4.7uF TDK
C2268
4.7uF
16V
C2189
3.3V_Proidiom
0
LGDT1129
R2574
GND
10K R2408
LGDT1129
1K
R1786
0
.1
u
F
16V
C
21
98
0.1uF
XMARK
C2267
PM_TS_VALID
001:AL20
XMARK_1.8V
MLB-201209-0120P-N2
L1230
TS_SYNC 001:AL17
BLM18PG121SN1D
XMARK
L1254
22 R1791
0
.1
u
F
16V
C
22
07
0
.1
u
F
16V
C
22
10
PM_TS_CLK
001:AL20
100 R2441
0
.1
u
F
16V
C
22
12
TS[1] 001:AL17
PM_TS[0-7]
001:AL19
DE_H_SYSCLK 012:C13
0
.1
u
F
16V
C
21
93
MSCL_3.3V
MSDA_3.3V
1K
R1787
M
L
B
-2
0
1
2
0
9
-0
1
2
0
P
-N
2
L
1
2
3
3
100 R2444
0
.1
u
F
16V
C
21
90
100 R2442
0
XMARK
R2590
10uF
6.3V
C2176
3.3V_Proidiom
TP2010
NFM18PS105R0J
6.3V
C2280
OUT IN
GND
3.3V_Proidiom
4.7uF
10V
C2268-*1
YUDEN
4.7uF
10V
C2271-*1
YUDEN
AZ1117BH-1.8TRE1
IC1240
XMARK
1
ADJ/GND
2 OUT 3
IN
LGDT1001
IC1209-*1
XMARK
H1 CLK1
B8 IO2_29/TP_SOP
B9 IO2_21/TP_VALID
B10
IO2_17/TP_ERR
C5 IO2_41/TP_DATA[7]
C6 IO2_36/TP_DATA[6]
C7
IO2_31/TP_DATA[5]
C8 IO2_25/TP_DATA[4]
C9 IO2_23/TP_DATA[3]
C10
IO2_18/TP_DATA[2]
C11 IO2_14/TP_DATA[1]
C12 IO2_8/TP_DATA[0]
M1
IO1_29
C3 IO1_2
C2 IO1_3
B1 IO1_4
G5
IO1_5
F4 IO1_6
D3 IO1_7
E4
IO1_8
F5 IO1_9
E3 IO1_10
D2
IO1_11
E2 IO1_12
G1 CLK0
B2
IO2_48/RESET
D14 IO3_37/I2C_SCK
E14 IO3_34/I2C_SDA
K4
DCLK
K13 CONF_DONE
H3 NCONFIG
J 4 NCE
H2
DATA0
G4 IO1_21SO
K3 IO1_22/ASDO
H4
NCEO
J13 NSTATUS
J 3 MSEL0
J 2
MSEL1
J14 TCK
H15 TDO
J15
TMS
H14 TDI
D4 IO1_1/INIT_DONE
D1
IO1_13
F3
IO1_14
G3 IO1_15
F2 IO1_16
E1
IO1_17
G2 IO1_18
F1 IO1_19
H5
IO1_20
J 1 IO1_23
K2 IO1_24
L3
IO1_25
K1 IO1_26
L1 IO1_27
L2
IO1_28
N1 IO1_30
M2 IO1_31
N2 IO1_32
M3
IO1_33
L5 IO1_34
M4 IO1_35
N 3
IO
1
_ 3
6
K 5
IO
1
_ 3
7
L 4
IO
1
_ 3
8
R 1
IO
1
_ 3
9
P 2
IO
1
_ 4
0
P 3
IO
1
_ 4
1
N 4
IO
1
_ 4
2
R 2
IO
4 _
1
T 2
IO
4 _
2
R 3
IO
4 _
3
P 4
IO
4 _
4
R 4
IO
4 _
5
T 4
IO
4 _
6
R 5
IO
4 _
7
M 5
IO
4 _
9
M 6
IO
4
_ 1
0
N 5
IO
4
_ 1
1
N 6
IO
4
_ 1
2
R 6
IO
4
_ 1
4
M 7
IO
4
_ 1
5
T 6
IO
4
_ 1
6
R 7
IO
4
_ 1
7
N 7
IO
4
_ 1
9
T 8
IO
4
_ 2
1
M 8
IO
4
_ 2
2
N 8
IO
4
_ 2
3
M 10
IO
4
_ 2
5
T 9
IO
4
_ 2
7
N 9
IO
4
_ 2
9
T 11
IO
4
_ 3
1
N 10
IO
4
_ 3
2
N 11
IO
4
_ 3
6
N 12
IO
4
_ 3
7
M 9
IO
4
_ 3
8
M 11
IO
4
_ 3
9
M 12
IO
4
_ 4
0
R 12
IO
4
_ 4
2
T 13
IO
4
_ 4
3
R 13
IO
4
_ 4
4
R 14
IO
4
_ 4
5
P 1
3
IO
4
_ 4
6
T 15
IO
4
_ 4
7
R 15
IO
4
_ 4
8
N 13
IO
3 _
1
P 1
4
IO
3 _
2
P 1
5
IO
3 _
3
R 16
IO
3 _
4
N 15
IO
3 _
5
N 16
IO
3 _
6
K 12
IO
3 _
7
K 14
IO
3 _
8
L 12
IO
3 _
9
N 14
IO
3
_ 1
0
M 13
IO
3
_ 1
1
M 14
IO
3
_ 1
2
L 13
IO
3
_ 1
3
M 15
IO
3
_ 1
4
M 16
IO
3
_ 1
5
L 14
IO
3
_ 1
6
L 15
IO
3
_ 1
7
L 16
IO
3
_ 1
8
K 16
IO
3
_ 1
9
K 15
IO
3
_ 2
0
J1
6
IO
3
_ 2
1
H16 CLK3
G16 CLK2
H12
IO3_22
G14 IO3_23
G13 IO3_24
G15 IO3_25
F16
IO3_26
F14 IO3_27
F13 IO3_28
F15
IO3_29
E16 IO3_30
E15 IO3_31
D16
IO3_32
D15 IO3_33
F12 IO3_35
E13
IO3_36
H13 IO3_38
G12 IO3_39
B16
IO3_40 C15
IO3_41
C14 IO3_42
D13 IO3_43
B15
IO2_1
A15 IO2_2
B14 IO2_3
C13
IO2_4
B13 IO2_5
A13 IO2_6
B12
IO2_7
A2 IO2_47
E12 IO2_9
E11
IO2_10
E9 IO2_11
D12 IO2_12
D11 IO2_13
B3
IO2_46
B11 IO2_15
A11 IO2_16
D10
IO2_19
A9 IO2_20
D9 IO2_22
C4
IO2_45
E10 IO2_24
B4 IO2_44
D8
IO2_26
E8 IO2_27
A8 IO2_28
D7
IO2_30
A4 IO2_43
B7 IO2_32
A6 IO2_33
E7
IO2_34
P12 IO4_41/CH_DATA[7]
P11 IO4_35/CH_DATA[6]
P10
IO4_33/CH_DATA[5]
P9 IO4_28/CH-DATA[4]
P8 IO4_24/CH_DATA[3]
P7
IO4_18/CH_DATA[2]
P6 IO4_13/CH_DATA[1]
P5 IO4_8/CH_DATA[0]
R10
IO4_30/CH_ERR
R9 IO4_26/CH_SOP
R8 IO4_20/CH_VALID
R11 IO4_34/CH_CLK
A
7
V
C
C
IN
T _1
A
10
V
C
C
IN
T _2
G
8
V
C
C
IN
T _3
G
10
V
C
C
IN
T _4
H
7
V
C
C
IN
T _5
H
9
V
C
C
IN
T _6
J8
V
C
C
IN
T _7
J1
0
V
C
C
IN
T _8
K
7
V
C
C
IN
T _9
K
9
V
C
C
IN
T _1
0
T
7
V
C
C
IN
T _1
1
T
10
V
C
C
IN
T _1
2
C
1
V
C
C
IO
1_
1
G
6
V
C
C
IO
1_
2
P
1
V
C
C
IO
1_
3
T
3
V
C
C
IO
4_
1
L
7
V
C
C
IO
4_
2
L
10
V
C
C
IO
4_
3
T
14
V
C
C
IO
4_
4
P
1
6
V
C
C
IO
3_
1
K
11
V
C
C
IO
3_
2
C
16
V
C
C
IO
3_
3
A
14
V
C
C
IO
2_
1
F
1
0
V
C
C
IO
2_
2
F
7
V
C
C
IO
2_
3
A
3
V
C
C
IO
2_
4
A
1
G
N
D _1
A
16
G
N
D _2
A
5
G
N
D _3
A
12
G
N
D _4
F
6
G
N
D _5
F
8
G
N
D _6
F
9
G
N
D _7
F
1
1
G
N
D _8
G
7
G
N
D _9
G
9
G
N
D
_1 0
G
11
G
N
D
_1 1
H
8
G
N
D
_1 2
H
10
G
N
D
_1 3
J7
G
N
D
_1 4
J9
G
N
D
_1 5
K
6
G
N
D
_1
6
K
8
G
N
D
_1 7
K
10
G
N
D
_1
8
L
6
G
N
D
_1
9
L
8
G
N
D
_2
0
L
9
G
N
D
_2
1
L
11
G
N
D
_2
2
T
1
G
N
D
_2
3
T
5
G
N
D
_2
4
T
12
G
N
D
_2
5
T
16
G
N
D
_2
6
J6
G
N
D
A _P
L
L 1
J5
G
N
D G
_P
L
L 1
J1
1
G
N
D A
_P
L
L 2
J1
2
G
N
D G
_P
L
L 2
H
6
V
C
C A
_P
L
L 1
H
11
V
C
C A
_P
L
L 2
B
6
IO
2 _
3 5
B
5
IO
2 _
4 2
D
6
IO
2 _
3 7
D
5
IO
2 _
3 8
E
6
IO
2 _
3 9
E
5
IO
2 _
4 0
22uF
10V
C2177
PM_TS[7]
TS[2]
PM_TS[4]
TS[1]
PM_TS[1]
TS[7]
PM_TS[5]
TS[5]
TS[6]
PM_TS[0]
PM_TS[6]
PM_TS[2]
TS[3]
TS[4]
PM_TS[3]
TS[0]
RESET
POWER
I2C
27MHz
12 P r o : i d i o m
XMARK_1.8V
Pro:Idiom (XMARK)
P L L v o l t a g e
INNER LAYER PATERN
LGDT1129 not use XMARK
XMARK LG1001(XMARK)
+VCCINT_1.5V
42LD6DDH-UA 2 0 1 1 . 1 2 . 0 1
Copyright ⓒ 2012 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only