Lexicon MPX 500, Руководство по обслуживанию

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Lexicon
6-1
Chapter 6 Theo r y of Operation
Schematic walkthrough
Sheet 1 (INPUT)
This sheet shows the input jacks, input amplifier (U12, U24) and A/D converter (U17) and their associated
circuits.
The MPX500 is fitted with both ¼” balanced phone and XLR input connectors for left and right input signals.
Inserting the ¼” phone plug on J11 or J12 will disconnect signals from XLR jack J10 and J13 respectively.
The following analog circuit description applies to the left signal channel; the function of the corresponding
components in the right channel is identical. Capacitors C42 and C43, along with ferrite beads FB10 and
FB11, prevent unwanted high frequency interference from entering of leaving through the input cables. DC
blocking is achieved by capacitors C74 and C79 in line with each leg of balanced signal path. R71, R72,
R74 and R75 along with C73 and C78 form a 6dB attenuator with a low-pass characteristic. Single stage
input amplifier U12 buffers the attenuated input and supplies gain, which is variable from about +9 to
+23dB, according to the setting of front-panel input trim control R149. The amplifier stage tends to balance
an unbalanced input, more so when operated at the higher gain needed for low level, unbalanced signal
sources. The differential signal from the amplifier is attenuated by R65-R68, ac coupled by C70 and C71,
and biased to 2.5VDC through R62 and R63. The bias voltage is developed from +5VA by the voltage
divider formed by R61 and R64, filtered by C68 and C69. The amplifier output is attenuated by about 18dB
to drive the differential input of the A/D converter, which has a full-scale sensitivity of about +7dBu. The
14dB trim range varies the resulting full-scale input sensitivity from 6dBV to +22dBu. Capacitors
C92 and C98 at the converter input serve to reduce ailing of spectral components at the 5 to 6MHz
oversampling frequency. The AK5383 (U17) is a 24bit, 128X over sampling 2 channel A/D converter
configured to produce serial digital audio in I2S format.
For information on the AK5383 see
http://www.akm.com/AKM/AKMprodinfo.htm
Sheet 2 (DAC)
This sheet shows the analog D/A converter (U11), filter and driver (U7, U8) and their associated circuits.
The 24 bit, 2 channel D/A converter CS4390 is configured to accept serial digital audio in I2S format. The
following analog circuit description is for the left channel; the function of the corresponding components in
the right channel is identical. The output of the converter feeds a differential multiple-feedback 2-pole low-
pass filter having a gain of about +12dB, formed by one section of dual op-amp U7 and associated
components. The other section of U7 inverts the single-ended filtered signal. The two outputs of U7 drive
the balanced output through series resistors R35 and R33, which isolate the amplifiers from capacitive
loads and present a differential output impedance of around 600 ohms. Output is available simultaneously
on the parallel-wired XLR and ¼” phone jack connectors, J6 and J7. If unbalanced output wiring is used
which grounds the ring of J7, R33 limits the current. Full-scale differential output from the converter is
2Vrms, or about +8dBu, which results in a full-scale output level of +26dBu balanced, +20dBu unbalanced.
Capacitors C24 and C26, along with ferrite beads FB6 and FB7, prevent unwanted high frequency
interference from entering or leaving through the output cables.
For information on CS4390 see http://www.cirrus.com/products/overviews/cs4380.html
Product data sheet (PDF) http://www.cirrus.com/ftp/pubs/4390.pdf
Sheet 3 (LEXICHIP3, ROM/RAM, uPROC)
This sheet shows the Z80 microprocessor (U13), EPROM (U9), EEPROM (U5), SRAM (U2), Audio DRAM
(U6) and digital signal processor Lexichip3 (U10) and their associated circuits.