Lenze EVS 9300 series, Системное руководство

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Function library
Working with function blocks
9-46
L
EDSVS9332S-D11 EN 3.0
9.1.4 Entries into the processing table
The 93XX controller provides a certain time for calculating the processing time of FBs. Since the type
and number of FBs to be used depends on the application and can vary strongly, not all available FBs
are permanently calculated. A processing table is therefore provided under code C0465, where only
the FBs used are listed. This means that the drive system is perfectly matched to the task. If further
function blocks are integrated into an existing configuration, these must be listed in the processing
table.
Several aspects must be observed:
The number of FBs to be processed is limited
A maximum of 50 FBs can be integrated into a configuration. Every FB requires a certain processing
time. Code C0466 displays the residual time for the processing of FBs. If this time has elapsed, no
further FBs can be integrated.
Entry sequence into the FBs
Normally, the entry sequence under C0465 is arbitrary, but it may be important for applications with
high response. In general, the most favourable sequence is adapted to the signal flow.
Example:
AND1
&
AND1-IN1
AND1-IN2
AND1-IN3
AND1-OUT
C0821/1
C0821/2
C0821/3
C0820/1
C0820/2
C0820/3
AND2
&
AND2-IN1
AND2-IN2
AND2-IN3
AND2-OUT
C0823/1
C0823/2
C0823/3
C0822/1
C0822/2
C0822/3
OR1
≥1
OR1-IN1
OR1-IN2
OR1-IN3
OR1-OUT
C0831/1
C0831/2
C0831/3
C0830/1
C0830/2
C0830/3
E1
E2
E3
E4
E5
1
0
C0114/1...5
DIGIN
DIGIN1
DIGIN2
DIGIN3
DIGIN4
DIGIN5
C0443
A1
A2
A3
A4
1
0
C0118/1...4
DIGOUT
DIGOUT1
DIGOUT2
DIGOUT3
DIGOUT4
C0117/1
C0117/2
C0117/3
C0117/4
C0444/4
C0444/3
C0444/2
C0444/1
FIXED0
FIXED1
Fig. 9-5 Example of a configuration
Structure of the processing table for the configuration example Fig. 9-5:
1. DIGIN does not have to be entered into the processing table
2. The first FB is AND1, since it receives its input signals from DIGIN and only has successors.
3. The second FB is OR1, since its signal source is the output of AND1 (predecessor). This
means that the output signal in AND1 must be generated first, before it can be processed in
OR1. At the same time, OR1 has a successor. This means that OR1 must be entered in the
processing table before the successor.
4. The third FB is AND2, since it has a predecessor (see 3.)