LeCroy LC564DL, Руководство по обслуживанию

Страница: 27 / 210

DRAM
The DRAM consists of two SIMM modules from 4 MB up to 32 MB each.
By interleaving two SIMMs, the access time is dramatically reduced (one beat every
30ns, while the other module “recovers” from the previous access).
The DRAM control logic, including refresh control, is built around several GALs and
a few gates.
RAMEUR (A44) is the main sequencer. It inserts refresh cycles whenever needed,
and drives row and column addressing timing.
RASADE (A39) controls the row address select lines of the memory modules, and
generates the addresses for double beat or burst accesses.
OCCASE (A37) generates the column address select lines of the SIMMs.
DRAME (A57) holds some glue logic, and a state machine that counts the number
of beats, inserting pauses in the access if necessary (single SIMM support).
Four multiplexers (A40, 42, 46 and 47) switch between odd and even addresses to
be sent to the address lines of the modules. One more multiplexer (A38) switches
low order address bits, routing them either directly to the processor, or to the DRAM
address generator in RASADE.
Normal Access Timing
This is the simplest access possible: the processor puts an address onto the
address bus, and reads back or writes one long word (32-bit wide) to DRAM.
Depending on the address (odd or even), bank A or bank B is selected in a dual
SIMM configuration.
Burst Access Timing
A burst access on a 603e configured as a 32-bit device, consists of either two
(“double beat”) or eight (“burst”) successive reads in DRAM. The idea is to put a
start address onto the address bus, and read back or write several data’s from or to
DRAM every clock cycle, without the processor incrementing the address (this is
done by the external logic). To increase system performance, the memory has
been interleaved, allowing each module to access a memory location every 60ns,
but with a delay of 30ns between the modules.
A burst access is signaled by an active low _TBST signal and a 32-bit access
(SIZ2..0= 011), a double-beat access is indicated by a high _TBST but an access
size of 64 bits (SIZ2..0= 100). The double-beat case is decoded by a GAL
(VIADUC), and the signal is named _DBEAT (active low).
Refresh Timing
The 32 kHz clock from the real time clock chip is used to refresh periodically the
DRAM.
The GAL RAMEUR generates the refresh cycles, as well as the sequencing of
_RAS and _CAS. Depending on the operating mode, it chooses to access slot A or
selects alternately slots A and B.
Theory of Operation 4-3