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Lavry DA2002 Скачать руководство пользователя страница 11

DA2002

Theory of Operation

9

Part II: Theory of Operation

The simplified block diagram (figure 1) shows the basic building blocks.

Oven Control

The PCM DAC is constructed of custom made laser trimmed thin film resistor networks;
yet any resistor is subject to short term drift due to temperature variations and long term
drift due to component aging. The resistor networks are kept at a constant temperature by
a linearly controlled heating element. (A bang-bang controller, such as a home thermostat
is undesirable because it produces turn on and turn off surges-- thus audible kicks.)
Keeping the resistors at constant temperature overcomes resistor dependency on
environmental temperature variations.

Figure 1

Calibration

A sequence where each resistor is tapped (one at a time) for voltage comparison against a
reference level tells the processor the required adjustments. The voltage difference
between any given network node and the reference is greatly amplified and then fed to a
strobing comparator (see multiplexers for calibration and error amplifier and comparator
gain blocks in the simplified diagram). The processor strobes the comparator and reads
its output. The strobing is repeated 4000 times for the sake of averaging out any error
due to amplifier noise. At the end of a comparator strobing cycle, the processor decides
whether to increase or decrease the specific voltage of the measured node. This is done
via the calibration 14 bit DACs (see diagram). Each calibration DAC is used as a 13 bit
device to ensure monotonic performance. Each DAC is fed to its corresponding node
through a large value resistor, thus a full 10V swing on the calibration DAC can only pull
a given node by +/-4mV, providing an effective adjustment of a part in 5 million per
calibration DAC step.

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Содержание DA2002

Страница 1: ...Model DA2002 High Resolution Digital to Analog Converter Operations Manual ...

Страница 2: ...Lavry Engineering Inc P O Box 4602 Rolling Bay WA 98601 360 598 9757 http www lavryengineering com E Mail techsupport lavryengineering com Revision 1 7C December 7 2011 ...

Страница 3: ...ormance and pure enjoyment of the artistic experience The no compromise approach of designer Dan Lavry to the architecture of the DA2002 resulted in a unique design with unparalleled accuracy As a classically trained musician he brings more than decades of engineering experience to his designs a lifetime of playing and listening to acoustic performance has honed his ability to discriminate subtle ...

Страница 4: ...omatic self calibration A large number of extra codes enable the addition of digital DC offset to the signal path without signal clipping The DC offset provides superior low level detail by keeping low level signals away from the most significant bit transitions A quad switch deglitcher circuit removes the unwanted transition glitch energy In both PLL Mode and CrystalLock Mode the DA2002 eliminate...

Страница 5: ...nal Connection 5 Analog Outputs 6 Analog Output Level 6 Turn On Sequence 7 Polarity Inversion 7 PLL Mode and CrystalLock Mode 8 Power and Fusing 8 Maintenance 8 Part II Theory of Operation Oven control 9 Calibration 9 Timing and Deglitcher 10 Jitter Removal 11 Output Filter and Drivers 11 Part III Specifications 12 Limited Warranty 13 ...

Страница 6: ...DA2002 Table of Contents 4 ...

Страница 7: ...CT between Search Mode and Manual Mode The mode selected is retained when power is removed In Search Mode each time the INPUT SELECT button is pressed the DA2002 will scan the inputs for the next input with a valid signal present It will skip the inactive input connectors where no signal is present The default setting is Search Mode enabled In Manual Mode each press of the INPUT SELECT button move...

Страница 8: ...d mode position the jumpers are set to 90 degrees with respect to the front panel Pin 1 of the XLR connectors is connected to ground potential for proper cable shield connection The LEFT OUTPUT and RIGHT OUTPUT IEC signals are always unbalanced and are not affected by J8 and J10 jumper settings Analog Output Levels The analog output level at the IEC connectors for a full scale digital input signal...

Страница 9: ...tive the unit steps through the input ports continuously as indicated by the input select lamps if in Search Mode Most DAC s contains relays for the purpose of muting the output during turn on allowing the DAC to settle to proper operating conditions The DA2002 contains no relays in order to avoid signal degradation associated with relay contacts The unit minimizes turn on spikes by incorporating ...

Страница 10: ...e through a small window in the hinged cover located next to the AC power switch and input connector To change or check the fuses or change the operating voltage carefully open the cover by lifting the right edge and pull the red fuse holder straight out of the power input module The voltage is set by turning the red fuse holder so the desired operating voltage is visible when the fuse holder s co...

Страница 11: ...mparison against a reference level tells the processor the required adjustments The voltage difference between any given network node and the reference is greatly amplified and then fed to a strobing comparator see multiplexers for calibration and error amplifier and comparator gain blocks in the simplified diagram The processor strobes the comparator and reads its output The strobing is repeated ...

Страница 12: ...l value The deglitcher circuit is in off state about half a sample time and on for the rest of the time The on time is the critical time and no digital activity takes place anywhere near the analog circuits The settled signals are fed to the output filter with minimum disturbance The deglitcher off time settling requires the circuit to block as much of the transitions from feeding forwards to the ...

Страница 13: ...hanged by tiny amounts 1ppm and not very often 15 seconds or more in a manner allowing it to track only very long term average drift Using such an approach with ordinary PLL will cause loss of lock because the slight variations in incoming data rate cause loss of correspondence between the input and the too steady of a clock circuit The DA2002 CrystalLock approach stores enough data in a dedicated...

Страница 14: ...k mode varispeed Crystal lock tracking 1ppm 15 seconds Channel separation 100dBFs at 1KHz Flatness response 05dB 10Hz 20KHz Phase linearity 2 degrees 10Hz 20KHz Digital inputs Two AES EBU 110 Ohm transformer isolated One Consumer 75 Ohm transformer isolated Analog outputs AES EBU balanced 4 2V R M S into 600 ohms AES EBU balanced 4 5V R M S into 100Kohms AES EBU unbalanced 2V R M S into 600 ohms A...

Страница 15: ...diction LIMITS AND EXCLUSIONS LAVRY ENGINEERING DOES NOT BY VIRTUE OF THIS AGREEMENT OR BY ANY COURSE OF PERFORMANCE COURSE OF DEALING OR USAGE OF TRADE MAKE ANY OTHER WARRANTIES EXPRESS OR IMPLIED INCLUDING WITHOUT LIMITATION ANY WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE OR NONINFRINGEMENT AND ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY DISCLAIMED LAVRY ENGINEERING EXPRESSLY...

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