
PowerTrace Serial User´s Guide
42
©1989-2018 Lauterbach GmbH
Recommendations for Target Board Design
•
Place the trace connector close to the target processor. Make sure that the ground and the latch
pins are connected to your target's ground plane.
For information on Samtec ERF8 connectors please refer to:
www.samtec.com
Additional information on flex extension cables can be obtained by contacting
[email protected].
•
Keep lane length short to keep attenuation caused by PCB material low.
•
Lane matching below 1cm (half inch) is sufficient, because it can be handled by the transmission
protocol.
•
+/- signal-matching must be done as good as possible. Make it on every direction-change even if
it is a very small difference. Further, the matching must be done before (seen from target to tool)
any layer change (via) happens.This keeps the best signal integrity.
•
Cut out the GND-plane below pads of connectors and components to reduce parasitic
capacitance.
•
Avoid stubs e.g. by using only top or bottom layers. Use back-drilled vias if middle layers are
used.
•
Ideally lanes should have a 100
impedance, but 5% tolerance is suitable. Use impedance
controlled PCBs. FR4-material is suitable for short distances (10cm/ 4inches).
•
Prevent use of signal vias. Ideally stay on one layer.
•
Place GND-stitching vias close to signal vias.
•
Don’t change the reference plane of the signals like e.g. GND->VCC->GND. Use only GND as
signal reference.
•
An adequate number of bypass capacitors for DUT are crucial to keep the supply voltage stable
when the trace port is driven by your application. If your supply voltages are not stable, the high-
speed trace signals might be instable too.
•
Capacitor vias should never be shared, each capacitor requires its own vias close to the pads.
•
The target voltage (VCCSENSE) has to be within the specified range, see
Electrical
requirements
. For other voltage levels, contact
.