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  MMDSP Debugger

 

    32     

  

©1989-2019 Lauterbach GmbH

Electrical Description of the 20-pin Debug Cable

•

The input and output signals are connected to a supply translating transceiver (74ALVC164245). 
Therefore the ICD/AICD can work in an voltage range of (1.5 V) 1.8 … 3.3 V (3.6 V). Please note 
that a 5 V supply environment is not supported! This would cause damage on the ICD/AICD. 
Please contact us for alternate solutions if you need to work with 5 V.

•

VTREF is used as a sense line for the target voltage. It is also used as supply voltage for the 
supply translating transceiver of the ICD/AICD interface to make an adaptation to the target 
voltage (1.5 V) 1.8 … 3.3 V (3.6 V).

•

 nTRST, TDI, TMS, TCK are driven by the supply translating transceiver. In normal operation 
mode this driver is enabled, but it can be disabled to give another tool access to the JTAG port. In 
environments where multiple tools can access the JTAG port, it is absolutely required that there 
is a pull down resistor at TCK. This is to ensure that TCK is low during a handover between 
different tools.

•

TDO is an ICD/AICD input. It is connected to the supply translating transceiver.

•

nRSTIN is used by the debugger to reset the target CPU or to detect a reset on the target. It is 
driven by an open collector buffer. A 47 k

 pull-up resistor is included in the ICD/AICD connector. 

The debugger will only assert a pulse on nSRST when the SYStem.UP, the SYStem.Mode Go or 
the SYStem.RESetOUT command is executed. If it is ensured that the DSP is able to enter 
debug mode every time (no hangup condition), the nSRST line is optional.

•

N/C (= Vsupply) is not connected in the ICD/AICD. This pin is used by debuggers of other 
manufacturers for supply voltage input. The ICD/AICD is self-powered.

There is an additional plug in the connector on the debug cable to the debug interface. This signal is tristated 
if the JTAG connector is tristated by the debugger and it is pulled low otherwise. This signal is normally not 
required, but can be used to detect the tristate state if more than one debug tools are connected to the same 
JTAG port.

Содержание MMDSP

Страница 1: ...nts 9 Software Breakpoints 9 On chip Breakpoints 10 On chip Breakpoints on instructions 10 Downloading Program Code to the Video Core 11 Changing the FLAG Register 11 Memory Classes 12 CPU specific SYStem Commands 14 SYStem CONFIG Configure debugger according to target topology 14 Daisy chain Example 16 TapStates 17 SYStem CONFIG CORE Assign core to TRACE32 instance 18 SYStem CPU Select the used C...

Страница 2: ...YStem Option OP9compatible Compatibility mode OP9 25 SYStem RESet Reset the system settings 26 SYStem Softreset Soft reset of the core 26 CPU specific Commands 27 Data LOAD Elf Load ELF file 27 Register RESet Soft reset 27 SNoop PC Enable PC snooping 28 CPU specific TrOnchip Commands 29 TrOnchip CONVert Adjust range breakpoint in on chip resource 29 TrOnchip VarCONVert Adjust complex breakpoint in...

Страница 3: ...ning training_debugger pdf Get familiar with the basic features of a TRACE32 debugger T32Start app_t32start pdf T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger T32Start is only available for Windows General Commands general_ref_ x pdf Alphabetic list of debug commands Architecture specific information Processor Architecture Manuals These ma...

Страница 4: ...the target while the target power is off 2 Connect the host system the TRACE32 hardware and the debug cable 3 Power ON the TRACE32 hardware 4 Start the TRACE32 software to load the debugger firmware 5 Connect the debug cable to the target 6 Switch the target power ON 7 Configure your debugger e g via a start up script Power down 1 Switch off the target power 2 Disconnect the debug cable from the t...

Страница 5: ...chip breakpoints in memory areas that are read only e g FLASH ROM If a program breakpoint is set within the specified address range on chip breakpoints are now used instead of software breakpoints A list of all available on chip breakpoints for your architecture can be found under On chip Breakpoints 6 Enter the debug mode This command resets the CPU and enters the debug mode After SYStem Up it is...

Страница 6: ...ad your application The load command depends on the file format generated by your compiler Be sure to load a file compiled for the correct core A full description of the Data Load command is given in the General Commands Reference Data Set DBG 0x1038 quad 0x0000000000200000 Data Set DBG 0x1050 quad 0x0080000000400000 Data Set DBG 0x1058 quad 0x0000000000C00000 PROG_BASE_ADR DATA_AHB_BASE DATA_AHB_...

Страница 7: ...MMDSP Debugger 7 1989 2019 Lauterbach GmbH Troubleshooting SYStem Up Errors No information available FAQ No information available No information available ...

Страница 8: ...POWER 7 9 V USB LAUTERBACH PODBUS OUT DEBUG CABLE Target PC or Workstation Ethernet Cable POWER SELECT EMULATE RECORDING TRIGGER ETHERNET CON ERR TRANSMIT RECEIVE COLLISION HUB 100 MBit Ethernet Debug Cable JTAG Connector DEBUG CABLE LAUTERBACH RESERVED FOR POWER TRACE C B A POWER DEBUG ETHERNET AC DC Adapter ...

Страница 9: ...xecution is stopped and the debug mode becomes active Software breakpoints can be set to instructions in RAM and with some preparations also to instructions in FLASH see FLASH Create and FLASH AUTO Software breakpoints on instructions in FLASH should only be used if the number of on chip breakpoints is insufficient The number of software breakpoints is unlimited STN8810A Audio note that modificati...

Страница 10: ...ata value is written to an address or when a specific data value is read from an address On chip Breakpoints on instructions On chip breakpoints are handled by the CPU internally and do not require to modify the program memory Therefore they can be used to set a breakpoint on an instruction in FLASH or ROM With the command MAP BOnchip range it is possible to instruct the debugger to use On chip br...

Страница 11: ...ly created while downloading the object code to the target The algorithm exploits the fact that some instructions do not use all fields of the opcode to obtain better compression While the functionality of an instruction is not affected by compression decompression a reconstructed opcode will not be necessarily binary identical to the original opcode Therefore the verify option for the data load c...

Страница 12: ...ysically overwritten by the new program The DBG memory class gives access to memory resources like host register indirect host registers and dictionary ram Video core only The mapping of these resources to addresses is arbitrary and does not relate to any MMDSP or system address mappings The mapping is only valid in the context of the DBG memory class To access a memory class write the class speci...

Страница 13: ... Note that for MMDSP it is not possible to access memory through the debugger while the core is executing code For not CPU specific keywords see non declarable input variables in ICE FIRE Analyzer Trigger Unit Programming Guide analyzer_prog pdf ...

Страница 14: ...lways only one debugger drives the signal lines TAPState and TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate mode Please note nTRST must have a pull up resistor on the target TCK can have a pull up or pull down resistor other trigger inputs need to be kept in inactive state Format SYStem CONFIG parameter number_or_address SYStem MultiCore parame...

Страница 15: ...the debugger IRPOST default 0 number of instruction register bits in the JTAG chain between the TDI signal and the core of interest This is the sum of the instruction register lengths of all TAPs between the TDI signal of the debugger and the core of interest TAPState default 7 Select DR Scan This is the state of the TAP controller when the debugger switches to tristate mode All states of the JTAG...

Страница 16: ...tion register length of Core A 3 bit Core B 5 bit Core D 6 bit SYStem CONFIG IRPRE 6 IR Core D SYStem CONFIG IRPOST 8 IR Core A B SYStem CONFIG DRPRE 1 DR Core D SYStem CONFIG DRPOST 2 DR Core A B SYStem CONFIG CORE 0 1 Target Core C is Core 0 in Chip 1 Core A Core B Core C Core D TDO TDI Chip 0 Chip 1 ...

Страница 17: ...erbach GmbH TapStates 0 Exit2 DR 1 Exit1 DR 2 Shift DR 3 Pause DR 4 Select IR Scan 5 Update DR 6 Capture DR 7 Select DR Scan 8 Exit2 IR 9 Exit1 IR 10 Shift IR 11 Pause IR 12 Run Test Idle 13 Update IR 14 Capture IR 15 Test Logic Reset ...

Страница 18: ...res have successive chip numbers at their GUIs Therefore you have to assign the coreindex and the chipindex for every core Usually the debugger does not need further information to access cores in none generic chips once the setup is correct Generic Chips Generic chips can accommodate an arbitrary amount of sub cores The debugger still needs information how to connect to the individual cores e g b...

Страница 19: ...rbach GmbH SYStem CPU Select the used CPU Selects the processor type Default selection STN8810A STN881xA is the Audio DSP STN881xV is the Video DSP Format SYStem CPU cpu cpu ST8810A ST8810V STN8815A STN8815V STN8820A STN8820V STN8820 I ...

Страница 20: ...CpuAccess mode mode Enable Denied Nonstop Enable For performing a memory access r w while the CPU is executing the debugger interrupts program execution briefly Each interruption takes 1 100 ms depending on the speed of the debug interface and on the number of the read write accesses required Window updates e g for data dump windows are on default performed 10 times s Denied The debugger is not al...

Страница 21: ...setting if possible SYStem LOCK Lock and tristate the debug port Default OFF If the system is locked no access to the debug port will be performed by the debugger While locked the debug connector of the debugger is tristated The main intention of the lock command is to give debug access to another tool Format SYStem JtagClock frequency ARTCK frequency SYStem BdmClock deprecated frequency 10000 400...

Страница 22: ...bles the debugger The state of the DSP remains unchanged The JTAG port is tristated No reset of the CPU NoDebug same as Down but CPU is running Go Same as Up but CPU is running Resets the CPU enables the debug mode and starts the user program immediately The program execution can be stopped manually or at a breakpoint On chip breakpoints can be used in Go mode On chip breakpoints have to be set be...

Страница 23: ...ables The mode can be set via the option sys o dcumode auto 24 16 In mode auto the mode is detected from the FLAGS register or the deduced from the stack frame In mode 16 or 24 all registers and variables are displayed in the chosen mode independently from the actual DCU mode of the CPU SYStem Option DIAG System diagnosis command System diagnosis command Execute only when demanded by LAUTERBACH su...

Страница 24: ...e single stepping Default OFF If enabled all interrupts will be masked during assembler single step operations by use of the EMU_UNIT_MASKIT register MMIO 0xF600 After the single step the register is restored to the original value If the option is disabled the EMU_UNIT_MASKIT register is not modified SYStem Option IMASKHLL Disable interrupts while HLL single stepping Default OFF If enabled all int...

Страница 25: ...ugger retrieves the value of pThis from the target memory everytime it uploads the registers values from the core The value of pThis is used to detect the currently active NMF module There is a pseudo register call pThis that is listed in the register window and can be accesses via the register function similar to actual core registers A pseudo register is an artificial register that has no corres...

Страница 26: ...Set Reset the system settings Reset all settings of the TRACE32 debugger to default values NOTE This does not reset the target system SYStem Softreset Soft reset of the core Performs a soft reset of the DSP core Format SYStem RESet Format SYStem Softreset ...

Страница 27: ...s the debugger performs a soft reset for setting the program counter to the program entry point at P 0x0 Register RESet Soft reset Sets all registers to their initial value after a reset This is done via soft reset of the core which may have effects besides updating the contents of architectural registers Format Data LOAD Elf filename Format Register RESet ...

Страница 28: ...RF METHOD StopAndGo is that for stopandgo the debugger will indicate real time violations red s in the bottom status line Also snooping is much faster than StopAndGo and thus done more frequently which results in a more detailed statistical analysis Format SNoop PC SNoop PC ON OFF SNoop PC Prints the current PC in the info line only once SNoop PC ON OFF Enables or disables that the debugger perman...

Страница 29: ...a complex variable the on chip break resources of the CPU may be not powerful enough to cover the whole structure If the option TrOnchip VarCONVert is set to ON the breakpoint will automatically be converted into a single address breakpoint This is the default setting Otherwise an error message is generated TrOnchip state Display on chip trigger window Opens the TrOnchip state window Format TrOnch...

Страница 30: ...MMDSP Debugger 30 1989 2019 Lauterbach GmbH TrOnchip RESet Set on chip trigger to default state Sets the TrOnchip settings and trigger module to the default settings Format TrOnchip RESet ...

Страница 31: ... 100 in We strongly recommend to use a connector on your target with housing and having a center polarization e g AMP 2 827745 0 A connection the other way around indeed causes damage to the output driver of the debugger Signal Pin Pin Signal VTREF 1 2 N C TRST 3 4 GND TDI 5 6 GND TMS 7 8 GND TCK 9 10 GND N C 11 12 GND TDO 13 14 GND RSTIN 15 16 GND N C 17 18 GND N C 19 20 GND ...

Страница 32: ...at there is a pull down resistor at TCK This is to ensure that TCK is low during a handover between different tools TDO is an ICD AICD input It is connected to the supply translating transceiver nRSTIN is used by the debugger to reset the target CPU or to detect a reset on the target It is driven by an open collector buffer A 47 k pull up resistor is included in the ICD AICD connector The debugger...

Страница 33: ...MMDSP Debugger 33 1989 2019 Lauterbach GmbH Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for MMDSP ICD LA 7836 1 8 3 6 V ...

Страница 34: ...supported yet CPU ICE FIRE ICD DEBUG ICD MONITOR ICD TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR A9500 YES YES YES A9540 YES YES YES DB8500 YES YES YES DB8540 YES YES YES STN8810 YES YES YES STN8815 YES YES YES STN8820 YES YES YES Language Compiler Company Option Comment C MMDSP STMicroelectronics ELF DWARF ...

Страница 35: ...logy Inc Windows UML DEBUGGER LieberLieber Software GmbH Windows SIMULINK The MathWorks Inc Windows ATTOL TOOLS MicroMax Inc Windows VISUAL BASIC INTERFACE Microsoft Corporation Windows LABVIEW NATIONAL INSTRUMENTS Corporation Windows TPT PikeTec GmbH Windows CANTATA QA Systems Ltd Windows RAPITIME Rapita Systems Ltd Windows RHAPSODY IN MICROC IBM Corp Windows RHAPSODY IN C IBM Corp Windows TESSY ...

Страница 36: ...debug and trace signals This is needed if you want to connect the Debug Cable without a Preprocessor and if there is only a Mictor on the target Suitable for MMDSP and ARC as well Order No Code Text LA 7836 JTAG MMDSP JTAGDebuggerforMMDSP ICD LA 7836A JTAG MMDSP A JTAGDebuggerLicenseforMMDSP LA 3722 CON JTAG20 MICTOR ARMConverterARM 20toMictor 38 Additional Options LA 7744A JTAG ARM10 A JTAG Debug...

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