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19

LatticeECP2 Standard Evaluation Board

Lattice Semiconductor

User’s Guide 

Table 38. SW1 Connections

SW2 is a momentary switch that, when pressed, forces the FPGA to start a configuration cycle.

SW3 is a momentary switch that the user can define for any purpose, such as a global reset. SW3 is wired to I/O
E18 (bank 1) and applies a low logic level (0) when pressed.

LEDs

Eight user-definable LEDs are provided on the top of the board under SW1. These LEDs are each wired to a sepa-
rate GPIO on bank 1 as defined in the Table 39. The current limiting resistors associated with these LEDs are wired
to 3.3V, but it is safe to drive these signals with any FPGA I/O voltage. The LED will light when its associated I/O pin
is driven low. 

Table 39. LED Connections

There are also three LEDs associated with the dedicated programming pins.

Table 40. Programming LEDs

Note: During JTAG programming, the state of the DONE LED has no meaning. This is because the DONE pin,
which drives the LED, is being controlled by the pin’s BSCAN cell. See Lattice technical note number TN1108,
LatticeECP2 sysCONFIG Usage Guide, for more information on the dedicated programming pins.

Seven-Segment Display

This board contains a seven-segment display, with decimal point, at U2. The segments are wired to GPIO as
defined in Table 41. A low on the pin will turn on the associated segment.

Switch

Pin

SW1-1

C12

SW1-2

B12

SW1-3

A11

SW1-4

A12

SW1-5

D12

SW1-6

E12

SW1-7

D13

SW1-8

E13

LED

Pin

D1

B14

D2

A14

D3

D14

D4

C13

D5

E14

D6

F14

D7

A13

D8

B13

LED

Pin

Color

Function

D12

PROGRAMN

Yellow

On when signal is low

D11

INITN

Red

On when initializing

D10

DONE

Green

On when configuration is complete

Содержание LatticeECP2

Страница 1: ...May 2007 Revision ebdug18_01 3 LatticeECP2 Standard Evaluation Board User s Guide ...

Страница 2: ...er or Target PCI 2 2 32 64 bit 33 66 MHz 3 3V PCI X 32 64 bit 66 133 MHz parity or ECC 3 3V Mode 1 RS 232 connector 33 33 MHz oscillator RJ 45 connector LCD connector Compact Flash connector Prototyping area with access to over 210 I O pins Optional SMA SMB connectors up to eight for high speed clock and data interfacing 7 segment display eight general purpose switches two momentary switches eight...

Страница 3: ...the output of the oscillator drives the primary clock at LatticeECP2 pin J21 this is the default position When pin 1 of the oscilla tor is aligned to pin 2 of the socket the clock is routed to LatticeECP2 pin J21 When using a half size oscillator align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock or align pin 1 of the oscillator to pin 5 of the socket to drive the PLL ...

Страница 4: ...ires on the cable See the Configuring Programming The Board section of this document for more information on this topic The pinouts for these headers are provided in the following tables Note A parallel port ispDOWNLOAD cable is included with each LatticeECP2 Standard Evaluation Board When using a parallel port 1x8 ispDOWNLOAD cable connect pin 1 of the cable to pin 1 of the 1x10 JTAG header For m...

Страница 5: ...10 PROGRAMN D7 11 12 Ground D6 13 14 Ground D5 15 16 Ground D4 17 18 Ground D3 19 20 Ground D2 21 22 Ground D1 23 24 Ground D0 25 26 Ground CSN1 27 28 WRITEN CS1N1 29 30 CFG0 Vcc Bank8 31 32 CFG1 Ground 33 34 CFG2 1 See section below on jumpers Function Pin Function CCLK 1 2 Ground N C 3 4 N C DOUT CSSON 5 6 N C N C 7 8 INITN DONE 9 10 PROGRAMN D7 11 12 Ground D6 13 14 Ground D5 15 16 Ground D4 17...

Страница 6: ... 1 to 2 J32 Open J9 Open J33 1 to 2 J10 Open J34 2 to 3 J11 Open J35 Open J13 Open J36 Open J17 1 to 2 J37 1 to 2 J18 1 to 2 J38 Open J19 Open J39 1 to 2 J22 Open J43 1 to 2 3 to 4 5 to 6 J23 Open J44 1 to 2 J24 Open Location Position Function Default J7 1 to 2 Multiple boards but not the last board in the chain 2 to 3 Single board or the last board in a chain X Determines the JTAG TDO path Locati...

Страница 7: ... or pull down on CS1N X Location Position Function Default J32 1 to 2 Pulls CSN high 2 to 3 Pulls CSN low Open No pull up or pull down on CSN X Location Position Function Default J33 1 to 2 Routes DI to J40 5 to support serial mode X 2 to 3 Routes data bit D 0 to J40 5 for SPIFAST support Location Position Function Default J34 1 to 2 Routes D 7 to J40 7 for SPI sysCONFIG support 2 to 3 Routes DOUT...

Страница 8: ...ed Open 1 Open 1 Jumper 0 Slave Parallel Open 1 Open 1 Open 1 Location Position Function Default J44 1 to 2 SPI fast read enables read op code 0x0B X Open SPI normal read enables read op code 0x03 All SPI Serial Flash shipped with this board support fast read This jumper must be removed when using the sysCONFIG par allel port Location Position Notes J31 Open See schematic J32 Open See schematic J3...

Страница 9: ...a current measuring device to be inserted between 1 2V and the FPGA core To measure current remove power from the board remove all of the jumpers at J30 install a meter between the odd pins and the even pins for example between pins 1 and 2 and apply power to the board When measurement is complete remove power from the board and re install all three jumpers Table 22 1 2V to VCC Core The header at ...

Страница 10: ...y the LatticeECP2 sysIO structures More infor mation can be found in Lattice technical note TN1102 LatticeECP2 sysIO Usage Guide available on the Lattice web site at www latticesemi com Table 25 Mixed Voltage I O Support For example if VCCIO is 3 3V then signals from devices powered by 1 2V 2 5V or 3 3V can be input and the thresholds will be correct assuming the user has also selected the desired...

Страница 11: ...VDS1 RSDS1 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18 Class I SSTL2 Class I II SSTL3 Class I II HSTL15 Class I HSTL18 Class I II SSTL18D Class I II SSTL25D Class I II SSTL33D Class I II HSTL15D Class I HSTL18D Class I II PCI33 LVDS25E1 LVPECL1 BLVDS1 RSDS1 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18 Class I SSTL2 Class I II SSTL3 Class I II HSTL15 Class I III HSTL18 Cl...

Страница 12: ...5 27 3 3V 28 PCI_AD22 W8 5 29 PCI_AD20 Y8 5 30 GND 31 PCI_AD18 V9 5 32 PCI_AD16 W9 5 33 3 3V 34 PCI_FRAME_N U10 5 35 GND 36 PCI_TRDY_N V10 5 37 GND 38 PCI_STOP_N W10 5 39 3 3V 40 PCI_SMBCLK TP8 PU if master 41 PCI_SMBDAT TP14 PU if master 42 GND 43 PCI_PAR Y10 5 44 PCI_AD15 W11 5 45 3 3V 46 PCI_AD13 U12 4 47 PCI_AD11 Y12 4 48 GND 49 PCI_AD9 W12 4 52 PCI_CBE0_N V12 4 53 3 3V 54 PCI_AD6 U13 4 55 PCI...

Страница 13: ...8 U16 4 72 GND 73 PCI_AD56 V16 4 74 PCI_AD54 T16 4 75 3 3V 76 PCI_AD52 Y16 4 77 PCI_AD50 W16 4 78 GND 79 PCI_AD48 Y17 4 80 PCI_AD46 W17 4 81 GND 82 PCI_AD44 Y18 4 83 PCI_AD42 W18 4 84 3 3V 85 PCI_AD40 Y19 4 86 PCI_AD38 Y20 4 87 GND 88 PCI_AD36 V17 4 89 PCI_AD34 V18 4 90 GND 91 PCI_AD32 U18 4 92 NC 93 GND 94 NC Note PD pull down resistor PU pull up resistor NC no connect TP test point Table 27 PCI ...

Страница 14: ... PCIX_ECC4 W3 5 11 PCI_PRSNT2_N J23 14 PCIX_ECC2 Y2 5 15 GND 16 PCI_CLK R1 6 D20 J22 17 GND 18 PCI_REQ_N Y3 5 19 3 3V 20 PCI_AD31 AB2 5 21 PCI_AD29 AA3 5 22 GND 23 PCI_AD27 AB3 5 24 PCI_AD25 AB4 5 25 3 3V 26 PCI_CBE3_N AA5 5 27 PCI_AD23 AB5 5 28 GND 29 PCI_AD21 AA6 5 30 PCI_AD19 AB6 5 31 3 3V 32 PCI_AD17 AB7 5 33 PCI_CBE2_N AA7 5 34 GND 35 PCI_IRDY_N AB8 5 36 3 3V 37 PCI_DEVSEL_N U11 5 38 PCIXCAP ...

Страница 15: ...CI_CBE6_N AB14 5 66 PCI_CBE4_N AA14 4 67 GND 68 PCI_AD63 AB15 4 69 PCI_AD61 AA15 4 70 3 3V 71 PCI_AD59 AB16 4 72 PCI_AD57 AA16 4 73 GND 74 PCI_AD55 AB17 4 75 PCI_AD53 AA17 4 76 GND 77 PCI_AD51 AB18 4 78 PCI_AD49 AA18 4 79 3 3V 80 PCI_AD47 AB19 4 81 PCI_AD45 AB20 4 82 GND 83 PCI_AD43 AA20 4 84 PCI_AD41 AB21 4 85 GND 86 PCI_AD39 AA22 4 87 PCI_AD37 AA21 4 88 3 3V 89 PCI_AD35 Y22 4 90 PCI_AD33 Y21 4 9...

Страница 16: ...ault J23 1 to 2 Master PCI PCI X Open Target PCI PCI X X Not installed If master also install R62 and C47 PCIXCAP J24 M66EN J38 Frequency Default PCI PCI X 1 to 2 2 to 3 33MHz 66MHz 1 to 2 Open 66MHz 66MHz Open 2 to 3 33MHz 133MHz Open Open 66MHz 133MHz X Don t Care 1 to 2 Master Master If master also install R126 and C111 Location Position Function Default J13 1 to 2 Target PCI PCI X X Open Maste...

Страница 17: ...h signal s test point a ground point has been added in order to make signal integrity measurements easier and more accurate Figure 3 Resistor Shorting Trace Table 36 Single Ended SI Test Points Location Position Function Default J22 1 to 2 Routes PCI_CLK to FPGA only used if installing this board in a PCI or PCI X backplane For signal integrity also remove R27 and R30 D20 provides PCI clamping for...

Страница 18: ...IOs placed nearby to allow for easy prototyping Please refer the schematics at the end of this document for more information Note that the test points for J21 and N21 have locations for zero ohm resistors R115 and R117 to allow isolation of the test points from the oscillator clock By default these resistors are not installed on the board Switches Switch 1 SW1 on the top edge of the board is an ei...

Страница 19: ... Table 39 LED Connections There are also three LEDs associated with the dedicated programming pins Table 40 Programming LEDs Note During JTAG programming the state of the DONE LED has no meaning This is because the DONE pin which drives the LED is being controlled by the pin s BSCAN cell See Lattice technical note number TN1108 LatticeECP2 sysCONFIG Usage Guide for more information on the dedicate...

Страница 20: ...y 16 are required for simple LCD panels If using an OPTREX 51505 or equivalent use pins 1 16 if using a LUMEX LCM S02002DSR or equivalent use pins 3 18 Two potentiometers are provided for LCD control R34 adjusts the backlight and R35 adjusts the contrast Power for the LCD panel is provided by the 3 3V to 5V converter at U7 Segment Pin A A15 B A17 C C15 D E15 E F15 F B15 G A16 DP D15 A G D E C B F ...

Страница 21: ...W A20 8 E E16 9 DB0 A18 10 DB1 C17 11 DB2 B18 12 DB3 C16 13 DB4 G16 14 DB5 B17 15 DB6 G15 16 DB7 B16 17 Anode R34 18 Cathode GND Table 43 Compact Flash Connector Signal J12 FPGA Pin J12 Signal GND 1 B11 26 CD1 D03 2 B10 A9 27 D11 D04 3 A10 C10 28 D12 D05 4 C11 F11 29 D13 D06 5 E11 A7 30 D14 D07 6 A8 B9 31 D15 CE1 7 B8 A6 32 CE2 A10 8 B7 D8 33 VS1 OE 9 C8 E10 34 IORD A09 10 D10 C6 35 IOWR A08 11 C7...

Страница 22: ...ns refer to Lattice technical note number TN1108 LatticeECP2 sysCONFIG Usage Guide SRAM Configuration The LatticeECP2 SRAM can be configured easily via the JTAG port The LatticeECP2 device is SRAM based so it must remain powered to retain its configuration when programming just the SRAM To program the SRAM perform the following procedure 1 Check that J7 and J8 are properly set see Table 6 and Tabl...

Страница 23: ...PGA device and render the board inoperable 3 Connect the LatticeECP2 Evaluation Board to an external 5V supply 4 Start the ispVM System software 5 Press the SCAN button located on the toolbar The LatticeECP2 device should be automatically detected The resulting screen should be similar to Figure 5 Figure 5 ispVM System Interface 6 Double click the device to open the device information dialog as sh...

Страница 24: ...ng the SPI Serial Flash 1 Install all three jumpers at J43 and the jumper at J44 This enables SPI mode by setting the CFG pins of the LatticeECP2 and it enables fast SPI reads Check that J7 and J8 are properly set see Table 6 and Table 7 and that J10 and J11 are open 2 Connect the download cable to J4 When using a 1x8 connector on the download cable connect to the 1x10 header by justifying the ali...

Страница 25: ...ck OK in both dialog boxes 7 Click on the green GO button on the ispVM toolbar to program the SPI Serial Flash 8 Press and release SW2 Program on the board to transfer the configuration data from the SPI Serial Flash to the LatticeECP2 The LatticeECP2 should now be running the new code Figure 7 SPI Serial Flash Dialog Box Ordering Information Technical Support Assistance Hotline 1 800 LATTICE Nort...

Страница 26: ...or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice Date Version Change Summary May 2006 01 0 Initial release March 2007 01 1 Added Ordering Information section April 2007 01 2 Added important information for proper connection of ispDOWNLOAD Programming Cables May 2007 01 3 Replaced two ...

Страница 27: ...of Doc B ECP2 Standard Block Diagram A 1 8 Title Size Document Number Rev Date Sheet of Doc B ECP2 Standard Block Diagram A 1 8 Bank 0 Bank 3 FPGA Bank 6 Bank 5 Bank 7 Bank 1 Bank 2 Bank 4 Lattice Semiconductor Corporation Area Prototyping Differential SI Testing 64 Bit PCI PCI X Single Ended SI Testing Power Supply Page 6 Page 6 Page 3 Page 2 Page 5 Page 4 JTAG for FPGA sysCONFIG LCD and Compact ...

Страница 28: ...2 32 41A B9 PT23 32 32 41B B8 PT24 33 33 42A A7 PT24 33 33 42B A8 PT25 34 34 43A F11 PT25 34 34 43B E11 PT26 35 35 44A C10 PT26 35 35 44B C11 PT27 36 36 45A A9 PT27 36 36 45B A10 VCCO1 G11 VCCO1 G12 VCCO1 G13 VCCO1 G14 VCCO0 G9 VCCO0 G10 VCCO0 H8 VCCO0 H9 PCLKT1_0 PT30 39 39 48A C12 PCLKC1_0 PT30 39 39 48B B12 PT31 40 40 49A A11 PT31 40 40 49B A12 PT33 42 42 51A D12 PT33 42 42 51B E12 PT34 43 43 5...

Страница 29: ...GDLLT_FB PR18 28 42 61A N20 GDLLC_FB PR18 28 42 61B N22 GPLLT_IN PR20 30 44 63AH N21 GPLLC_IN PR20 30 44 63BH P21 GPLLT_FB PR21 31 45 64A P22 GPLLC_FB PR21 31 45 64B R20 VREF1_3 PR16 22 28 47A L21 VREF2_3 PR16 22 28 47B M20 PRNC 23 29 48AH H22 PRNC 23 29 48BH J22 PR22 32 46 65AH P19 PR22 32 46 65BH P18 PR23 33 47 66A R21 PR23 33 47 66B R22 PR2 2 2 2AH VREF1_2 E19 PR2 2 2 2BH VREF2_2 D19 PRNC 4 10 ...

Страница 30: ...4 33 33 42B W11 PB25 34 34 43B AA12 PB26 35 35 44B PCLKC5_0 AB14 PCLKT4_0 PB31 40 40 49A U12 PB32 41 41 50A Y12 BDQS PB33 42 42 51A AA13 PB34 43 43 52A U13 PB35 44 44 53A AB15 PB36 45 45 54A AB16 PB37 46 46 55A W13 PB39 48 48 57A AB18 PB40 49 49 58A V14 PB41 50 50 59A Y15 BDQS PB42 51 51 60A AA16 PB43 52 52 61A AB20 PB44 53 53 62A U15 PB45 54 54 63A Y16 PB46 55 55 64A AA18 PB48 57 66 75A AA21 PB49...

Страница 31: ... 0 01uF CC0603 R101 10 R101 10 TP_M4 TP_M4 TP_VCC17 TP_VCC17 TP_M3 TP_M3 R12 DNL R12 DNL R86 DNL R86 DNL TP_VCC15 TP_VCC15 TP_SI7 TP_SI7 TP_GND10 TP_GND10 TP_M1 TP_M1 TP_T6 TP_T6 TP_G2 TP_G2 R15 DNL R15 DNL TP_SI0 TP_SI0 R84 DNL R84 DNL R4 DNL R4 DNL TP_GND15 TP_GND15 TP_R4 TP_R4 TP_GSI1 TP_GSI1 C57 0 01uF CC0603 C57 0 01uF CC0603 TP_J6 TP_J6 TP_U2 TP_U2 TP_GND11 TP_GND11 J17 HEADER 3X2 J17 HEADER...

Страница 32: ...lled 8 Load one Flash not both Configuration Status A1 A2 B2 B1 sysCONFIG Connectors U5 W25P32VSFIG U5 W25P32VSFIG HOLD 1 VCC 2 N C1 3 N C2 4 N C3 5 N C4 6 S 7 Q 8 W 9 VSS 10 N C5 11 N C6 12 N C7 13 N C8 14 D 15 C 16 J43 HEADER 3X2 J43 HEADER 3X2 2 4 6 1 3 5 J44 HEADER 2 J44 HEADER 2 1 2 SW2 SW PUSHBUTTON SW2 SW PUSHBUTTON A1 B1 A2 B2 J7 J7 1 2 3 C35 0 1uF CC0603 C35 0 1uF CC0603 JB22 JBLOCK JB22 ...

Страница 33: ...6 U3F ECP2 12 22 35 50 fpBGA484 6 of 6 U3F ECP2 12 22 35 50 fpBGA484 VCC CORE J10 VCC CORE J11 VCC CORE J12 VCC CORE J13 VCC CORE K9 VCC CORE K14 VCC CORE L9 VCC CORE L14 VCC CORE M9 VCC CORE M14 VCC CORE N9 VCC CORE N14 VCC CORE P10 VCC CORE P11 VCC CORE P12 VCC CORE P13 XRES 10K 1 to GND F12 GND A1 VCCAUX C5 VCCAUX D11 VCCAUX E6 VCCAUX E17 VCCAUX F13 VCCAUX G5 VCCAUX G18 VCCAUX K5 VCCAUX M17 VCC...

Страница 34: ... 1 EN 7 SS 8 SW 3 FB 5 GND 4 COMP 6 PAD 9 J47 PWR JACK J47 PWR JACK 3 2 1 D15 1N5820 267 05 D15 1N5820 267 05 R38 26 1K 1 CR0603 R38 26 1K 1 CR0603 C21 47uF SizeB C21 47uF SizeB C25 2 2uF CC0805 C25 2 2uF CC0805 J45 CONN_BLACK J45 CONN_BLACK S 1 R45 200K R45 200K R36 500K R36 500K 1 3 2 GND22 HEADER 1 GND22 HEADER 1 1 U8 TPS64203DVB SOT23 6 U8 TPS64203DVB SOT23 6 EN 1 GND 2 FB 3 ISENSE 4 VIN 5 SW ...

Страница 35: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice LS E2 L BASE PC N ...

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