Lattice CrossLink LIF-MD6000 Master Link Board - Revision C, Руководство пользователя

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CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 13
6. SMA IO Link Board
The SMA IO Link board connects to the CrossLink LIF-MD6000 Master Link Rev C board’s Tx or Rx connectors (U7, U9,
U11 or U12) and transfers signals to the respective SMA connectors.
Table 6.1. Headers and Test Connectors
Part Description Mapping to U1
J1 SMA connector for DCK_TX_P Pin 1
J2 SMA connector for DCK_TX_N Pin 2
J3 SMA connector for DATA0_TX_P Pin 4
J4 SMA connector for DATA0_TX_N Pin 5
J5 SMA connector for DATA1_TX_P Pin 7
J6 SMA connector for DATA1_TX_N Pin 8
J7 SMA connector for DATA2_TX_P Pin 13
J8 SMA connector for DATA2_TX_N Pin 14
J9 SMA connector for DATA3_TX_P Pin 16
J10 SMA connector for DATA3_TX_N Pin 17
J11 SMA connector for DATA4_TX_P Pin 24
J12 SMA connector for DATA4_TX_N Pin 25
J13 SMA connector for DATA5_TX_P Pin 27
J14 SMA connector for DATA5_TX_N Pin 28
U1 Connector to interface to CrossLink Master Link Rev C board N/A
Table 6.2. U1 Connector Description
Pin Name
1 CH4_DCK_P
2 CH4_DCK_N
3 GND
4 CH4_DATA0_P
5 CH4_DATA0_N
6 GND
7 CH4_DATA1_P
8 CH4_DATA1_N
9 GND
10 SN
11 SCLK
12 GND
13 CH4_DATA2_P
14 CH4_DATA2_N
15 GND
16 CH4_DATA3_P
17 CH4_DATA3_N
18 GND
19 12V
20 12V
Pin Name
21 TBD
22 RESETN
23 PWR_5-0V
24 GND
25 GND
26 PWR_3-3V
27 GND
28 GND
29 PWR_1-8V
30 MOSI
31 MISO
32 PWR_1-8V
33 GND
34 GND
35 PWR_3-3V
36 GND
37 GND
38 PWR_5-0V
39 SDA
40 SCL
Note : U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link Rev C
board connector this daughter board is connected to.