Lattice Semiconductor MachXO5-NX Development Kit, Руководство пользователя

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MachXO5-NX Development Board
Preliminary Evaluation Board User Guide
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14 FPGA-EB-02052-0.90
The MachXO5-NX Development Board also provides test points for other dedicated JTAG configuration pins as shown
in
Table 3.2 .
Table 3.2. Other Config JTAG Control Signals
Net Name MachXO5-25 Ball Location LED Indicator Test Point
JTAGEN B20 — Pin 1 of JP2
PROGRAMN F12 — Pin 1 of JP5
INITN E13 D11 TP5
DONE F13 D10 TP6
JP2 for JTAGEN is used to pull down the JTAGEN for enabling JTAG port when JTAG_PORT is disabled by software. JP5
can bridge push button PB4 with PROGRAMN when PROGRAMN_PORT function is enabled by software.
3.2. I
2
C Download Interface
The USB hub on the PC can also detect the addition of the USB function on Config FTDI Port B and you can select the
port FTUSB-1 on the programmer interface for the accessing from Config FTDI Port B to the MachXO5-25 dedicated I
2
C
download port ( Figure 3.2 ) that is named as FTDI_SDA/FTDI_SCL with 2.2 kΩ pull up resistor each. The Diode D21 is
inserted to support I
2
C clock stretching mode. Figure 3.5 details the design of Config FTDI Port B for dedicated I
2
C
download interface. Table 3.3 summarizes the interconnection with MachXO5-25 and its supported circuits. JP12 and
JP13 are used to connect the dedicated I
2
C download port of MachXO5-25 with the bridge I
2
C bus SDA0/SCL0 cross the
whole board, in case you need access I
2
C download port from other on board headers other than Config FTDI part. For
the detail connection from other headers to bridge I
2
C bus SDA0/SCL0, refer to the User I2C Interface section.
Figure 3.5. I
2
C Programming Mode
Table 3.3. Download I
2
C Connections
Download I
2
C Net Name
MachXO5-25 Ball
Location for JTAG
2.2 kΩ Pull up Resistor
Bridge I 2 C Net
Name
Bridge Jumper
FTDI_SCL G15 R33 SCL0 JP12
FTDI_SDA F15 R34 SDA0 JP13
For more information on MachXO5-25 JTAG/ I
2
C programming, refer to MachXO5-NX Programming and Configuration
User Guide (FPGA-TN-02271) .