MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-202
2
Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
FPGA-EB-02051-2.3
NC
IO0
109
110
111
112
GND
GND
113
114
115
117
119
120
GND
GND
121
122
125
126
127
128
GND
GND
130
131
132
133
136
137
GND
GND
138
139
140
141
142
143
GND
GND
1
2
J2
3.3
IO3
3.3
NC
1
2
3
4
5
6
9
10
GND
GND
11
12
13
14
GND
GND
19
20
21
22
GND
GND
23
24
25
26
GND
GND
27
28
GND
GND
32
33
34
35
1
2
J4
Top Side
J2
J4
LC
M
XO
2
-7
0
00
HE
4
TG
144
C
Figure 7.2. J3/J4 Header Landing Callout
LC
M
XO
2
-7
0
00
HE
4
TG
144
C
1.2
IO1
1.2
NC
74
73
76
75
GND
GND
78
77
82
81
GND
GND
84
83
86
85
GND
GND
92
91
94
93
GND
GND
96
95
98
97
GND
GND
100
99
105
104
107
106
1
2
J3
NC
IO2
71
69
70
68
67
62
65
61
GND
GND
60
58
59
57
GND
GND
56
54
55
52
GND
GND
50
48
49
47
GND
GND
45
43
44
42
GND
GND
41
39
40
38
1
2
J5
J3
J5
Top Side
Figure 7.3. J3/J5 Header Landing Callout
