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an6079_01.0

 

August 2008

Application Note AN6079

 

© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

 

Introduction

 

Lattice ispClock™5620A and ispClock5610A are in-system programmable zero delay clock generator ICs with inte-
grated universal fan-out buffers. In some applications these devices are required to generate multiple clock output
frequencies from a single reference oscillator clock source.

The input to output clock phase relation is guaranteed only when the reference clock high pulse width or low pulse
width are greater than the data sheet t

 

CLOCKHI

 

 and t

 

CLOCKLOW

 

 specifications. If either specification is violated the

input to output clock phase relationship can be restored by activation of the RESET pin of the ispClock 5600A
device. This application note examines two common conditions when the reference oscillator clock could violate
the t

 

CLOCKHI

 

 or t

 

CLOCKLOW

 

 specifications and warrant the activation of the RESET pin.

 

Powering Up Reference Oscillator After ispClock5600A

 

Figure 1 details the start-up behavior of a typical oscillator module. Note that for the first 50ms the output is active,
the amplitude and offset are ramping up. It is during this time that the ispClock may see a very narrow clock pulse
because the thresholds at the ispClock inputs are fixed but the oscillator output is changing. In this case the
RESET pin of the ispClock should be activated after the oscillator output is stable.

 

Figure 1. Powering Up a Reference Oscillator

 

Oscillator Enabled Asynchronously

 

Figure 2 shows the general behavior of a typical oscillator module when the output enable pin is controlled by an
asynchronous enable signal. The output is held low when the enable pin is low and oscillates when the enable pin
goes high. Figure 3 zooms in on the initial output transitions and reveals two short pulses that would result in a tim-
ing violation for the reference clock input of the ispClock.

 

Interfacing ispClock5600A with

Reference Clock Oscillators

Содержание ispClock5620A

Страница 1: ...k 5600A device This application note examines two common conditions when the reference oscillator clock could violate the tCLOCKHI or tCLOCKLOW specifications and warrant the activation of the RESET pin Powering Up Reference Oscillator After ispClock5600A Figure 1 details the start up behavior of a typical oscillator module Note that for the first 50ms the output is active the amplitude and offset...

Страница 2: ...d Figure 3 Initial Transitions of Enabled Oscillator In this case where the reference oscillator is gated on either by the output enable pin of the oscillator or by other means of asynchronous enable the RESET pin should be activated after the reference has been enabled and the clock input to the ispClock is stable ...

Страница 3: ...e ispClock device to accept clock pulses that are much shorter than the tCLOCKHI or tCLOCKLOW specifications without resulting in unpredictable input to output phase relationships The M and N dividers can be placed in bypass mode by checking the box in the PLL Core Settings dialog box of PAC Designer which is shown in Figure 4 Placing M and N into bypass mode results in a divider value of unity fo...

Страница 4: ...ce Clock Oscillators 4 Technical Support Assistance Hotline 1 800 LATTICE North America 1 503 268 8001 Outside North America e mail isppacs latticesemi com Internet www latticesemi com Revision History Date Version Change Summary August 2008 01 0 Initial release ...

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