iCE40 Oscillator Usage Guide
Technical Note
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10
FPGA-TN-02008-1.7
A.4. HSOSC Usage in Lattice Radiant Software
Parameter Values
The HSOSC primitive has the following parameter options:
Parameter CLKHF_DIV = "0b00" (default), "0b01", "0b10", "0b11" (Clock divider selection. 0b00 = 48 MHz, 0b01 = 24 MHz, 0b10 = 12
MHz, 0b11 = 6 MHz)
Verilog Instantiation
HSOSC
#(
.CLKHF_DIV ("0b00")
) OSCInst0 (
.CLKHFEN (ENCLKHF),
.CLKHFPU (CLKHF_POWERUP),
.CLKHF (CLKHF)
);