Lattice Semiconductor iCE40 SPRAM Series, Техническая заметка

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iCE40 SPRAM Usage Guide
Technical Note
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TN1314-1.0 7
Use Cases for User Primitive SB_SPRAM256KA 4.
This section describes the use cases of the SB_SPRAM256KA RAM blocks while instantiating, inferring, and cascading
these blocks.
4.1. Instantiating Memories
SB_SPRAM256KA primitive can be directly instantiated using both Verilog and VHDL at the top level. An example of
instantiating SB_SPRAM256KA RAM using Verilog:
// spram256 user modules //
SB_SPRAM256KA ramfn_inst1(
.DATAIN(DATAIN),
.ADDRESS(ADDRESS),
.MASKWREN(MASKWREN),
.WREN(WREN),
.CHIPSELECT(CHIPSELECT),
.CLOCK(CLOCK),
.STANDBY(STANDBY),
.SLEEP(SLEEP),
.POWEROFF(POWEROFF),
.DATAOUT(DATAOUT_A)
)
SB_SPRAM256KA ramfn_inst2(
.DATAIN(DATAIN),
.ADDRESS(ADDRESS),
.MASKWREN(MASKWREN),
.WREN(WREN),
.CHIPSELECT(CHIPSELECT),
.CLOCK(CLOCK),
.STANDBY(STANDBY),
.SLEEP(SLEEP),
.POWEROFF(POWEROFF),
.DATAOUT(DATAOUT_B)
)
4.2. Inferring Memories
The memory also supports memory inferring where a behavioral code for the SPRAM is synthesized in iCEcube2 to
create the RAM using the RAM primitives of ICE40 device. In order to use SB_SPRAM256KA RAM blocks, users can use
syn_ramstyle attribute.
The power save states (Standby, Sleep, and Power Off States) are not available when inferring the RAM. When
implementing the inferred RAM using SB_SPRAM256KA primitives, software should tie off the STANDBY, SLEEP and
SHUTDOWN ports to “0”. If power save features are desired, then users should use the method of instantiation and
connect these ports as per design requirements.
4.3. Output Pipeline Registers
The SB_SPRAM256KA does not include output registers.
When desired, pipeline registers are required to be implemented in the fabric. While inferring the RAM, the software
should implement the output pipeline registers in the fabric.