Lattice Semiconductor iCE40 SPRAM Series, Техническая заметка

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iCE40 SPRAM Usage Guide
Technical Note
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6 TN1314-1.0
Power Save States for SPRAM 3.
The iCE40 provides a capability to place the SPRAM in a different power state, when not in use. There are three user
signals that control the power states of the RAM.
3.1. Normal State
Normal State is the normal operation of the memory. During this state, all three of the power save signals (STANDBY,
SLEEP and SHUTDOWN) are being driven Low. This is also the higher power consumption state of the SPRAM.
3.2. Standby State
Standby State is achieved when the STANDBY signal is driven High. When active, the memory goes in a low leakage
mode. The state of the outputs does not change when the RAM is placed in Standby State.
It is to be noted that Standby State is referred to as “Light Sleep” state in the RAM datasheet. The name STANDBY has
been chosen to match and be consistent with the power states for the Lattice Power Management Unit (PMU).
3.3. Sleep State
Sleep State is achieved when the SLEEP signal is driven High. This signal shuts down the power to the periphery of the
memory and maintains the memory contents. The outputs in this case are all pulled Low.
Sleep State is referred to as “Deep Sleep” state in the RAM datasheet. The name SLEEP has been chosen to match and
be consistent with the power states for the Lattice Power Management Unit (PMU).
3.4. Power Off State
Each RAM block has a power switch associated with it, and that power switch controls the SD signal of the RAM. Users
will be interfacing through CIB to the Power Switch and that will power down the memory.
Shut Down or Power Off State is achieved when the POWEROFF signal is driven Low. This signal shuts down the power
to the periphery of the memory and the memory core. In this state, there is no data retention of the memory. The
outputs in this case are all pulled low.