CrossLink Programming and Configuration Usage Guide
Technical Note
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. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-TN-02014-1.2
9
4.4.
Configuration
The FPGA is able to accept the configuration bitstream created by the Lattice Diamond
®
development tools.
CrossLink begins fetching configuration data from non-volatile memory. The memory used to configure CrossLink is
either the internal NVCM, or an external SPI Flash.
During configuration, the external SPI Flash is accessed in MSPI mode in the following two cases:
Case 1: At HW default state, with NVCM-EXT boot up sequence.
Case 2: If the BOOT_UP_SEQUENCE configuration option has been set as EXT, NVCM-EXT, EXT-NVCM and EXT-EXT
in the device feature row, the configuration engine uses the MSPI mode. The only setting for BOOT_UP_SEQUENCE
that does not use the MSPI mode is NVCM.
Note
: The MSPI persistence has no effect with the availability of MSPI mode to the configuration engine during device
configuration.
CrossLink does not leave the Configuration state if there are no memories with valid configuration data. In this case,
only the SSPI and I
2
C modes may be used to program the device when it is in a blank/erased state. An external SPI
Master or I2C Master needs to write the Activation Key to the FPGA while CRESETB is held LOW and within 9.5 ms from
V
CC
min during power up to enter into SSPI or Slave I
2
C mode.
4.5.
Wake-up
Wake-up is the transition from configuration mode to User Mode. CrossLink’s fixed four-phase Wake-up sequence
starts when the device has correctly received all of its configuration data. When all configuration data is received, the
FPGA asserts an internal DONE status bit. The assertion of the internal DONE causes a Wake-up state machine to run
that sequences four controls. The four control strobes are:
External CDONE
Global Write Disable (GWDIS)
Global Output Enable (GOE)
Global Set/Reset (GSR)
In the first phase of the Wake-up process at default software settings, CrossLink releases the Global Output Enable and
asserts the Global Write Disable.
When Global Output Enable is asserted, it permits the FPGA’s I/O to exit a high-impedance state and take on their
programmed output function. The FPGA inputs are always active. The input signals are prevented from performing any
action on the FPGA flip-flops by the assertion of the Global Set/Reset (GSR).
The Global Write Disable is a control that overrides the write enable strobe for all RAM logic inside the FPGA. The
inputs on the FPGA are always active, as mentioned in the Global Output Enable section. Keeping GWDIS asserted
prevents accidental corruption of the instantiated RAM resources inside the FPGA.
The second phase of the Wake-up process releases the Global Set/Reset and the Global Write Disable controls.
The Global Set/Reset is an internal strobe that, when asserted, causes all I/O flip-flops, Look Up Table (LUT) flip-flops,
distributed RAM output flip-flops, and Embedded Block RAM output flip-flops that have the
GSR enabled
attribute to
be set/cleared per their hardware description language definition.
The last phase of the Wake-up process is to assert the external CDONE pin. The CDONE pin may also be held LOW
externally to delay the User Mode entry in order to synchronize with other devices. This behavior is configurable, see
the
section on page 10 for details on the CDONE pin.
When the final Wake-up phase is complete, the FPGA enters User Mode.
4.6.
User Mode
CrossLink enters User Mode immediately when the Wake-up sequence has completed. User Mode is the point in time
when CrossLink begins performing the logic operations you designed. CrossLink remains in this state until the
configuration memory is cleared or power is lost.
