AWARD BIOS SETUP
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Bank 0/1 DRAM Timing / Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing / Bank 6/7 DRAM Timing :
The DRAM timing is controlled by
the DRAM Timing Registers. The Timings programmed into this register are dependent
on the system design. Slower rates may be required in certain system designs to
support loose layouts or slower memory.
DRAM Clock :
The chipset support synchronous and asynchronous mode between the
host clock and DIMM clock.
Host CLK (default)
DIMM clock equal to host clock
66MHz
DIMM clock equal to 66MHz
SDRAM Cycle Length :
This item allows you to select the SDRAM cycle length. The
settings are 2 or 3.
Memory Hole :
In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory space below
16MB.
Enabled
Memory hole supported
Disabled (default)
Memory hole not supported
P2C / C2P Concurrency :
This item allows you to Enable or Disable the PCI to CPU,
CPU to PCI concurrency. The default setting is “Enabled”.
System BIOS Cacheable :
Selecting “Enabled” allows caching of the system BIOS ROM
at F0000h – FFFFFh, resulting in better system performance. However, if any program
writes to this memory area, a system error may result. The settings are “Enabled” and
“Disabled”.
Video RAM Cacheable :
Select “Enabled” allows caching of the video BIOS, resulting in
better system performance. However, if any program writes to this memory area, a
system error may result. The settings are: “Enabled” and “Disabled”.
AGP Aperture Size :
Select the size of the Accelerated Graphics Port (AGP) aperture.
The aperture is a portion of the PCI memory address range dedicated for graphics
memory address space. Host cycles that hit the aperture range are forwarded to the
AGP without any translation.
