Lanner electronics IMB-X60 Series, Руководство пользователя

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Chapter 3 BIOS Setup
30
User’s Manual
DRAM Timing By SPD:
This item allows you to select the value in this field, depending on whether the board
has paged DRAMs or EDO (extended data output) DRAMs.
SDRAM Cycle Length:
This item allows you to select the SDRAM cycle length. The settings are 2 or 3.
Bank Interleave:
Select the bank interleave. The default setting is Disabled .
Memory Hole:
In order to improve performance, certain space in memory can be reserved for ISA cards.
This memory must be mapped into the memory space below 16MB.
P2C / C2P Concurrency: This item allows you to Enable or Disable the PCI to CPU, CPU to PCI concurrency.
The default setting is Enabled .
Fast R-W Turn Around: This setting activates or deactivates a timing rapid of the cycles of lettura-scrittura.
If memories of low quality are used or a system bus specifies outside deactivating this mode, not to have
problems of instability of the system is advisable. Activating it with memories to high performance is possible.
It is not possible to pretend resulted convincing from desks of memory of low quality.
System BIOS Cacheable: Selecting Enabled allows caching of the system BIOS ROM at F0000h - FFFFFh,
resulting in better system performance. However, if any program writes to this memory area, a system error
may result. The settings are
Enabled and Disabled .
Video RAM Cacheable: The choices: Enabled(Default) and Disabled.
Frame Butter Size:
The choices: 2M, 4M, and 8M(Default).
AGP Aperture Size:
Select the size of the Accelerated Graphics Port (AGP) aperture. The aperture is a
portion of the PCI memory address range dedicated for graphics memory address space. Host cycles that hit
the aperture range are forwarded to the AGP without any translation. The choices: 128M, 64M, 32M, 16M, 8M,
and 4M.
CPU to PCI Write Buffer: When this field is Enabled , writes from the CPU to the PCI bus is buffered, to
compensate for the differences between the CPU and the PCI bus. When disabled, the writes are not
buffered and the CPU must wait until the write is complete before starting another cycle. The default setting
is
Enabled .
PCI Dynamic Bursting: This item allows you to enable or disable the PCI dynamic bursting function. The
settings are Enabled or Disabled .