Lanner electronics IAC-F847 Series, Руководство пользователя

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Chapter 3. Bios Setup
27
User’s Manual
3.5 Chipset Features Setup
When you select the CHIPSET FEATURES SETUP on the main program, the screen display will appears as:
Chipset Features Setup Screen
Phoenix - Award BIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
Menu Level
!
Spread Spectrum
DRAM Timing Selectable
CAS Latency Time
Active to Precharge Delay
DRAM RAS# to CAS# Delay
DRAM RAS# Precharge
Turbo Mode
Memory Frequency For
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
Delayed Transaction
Delay Prior to Thermal
AGP Aperture Size (MB)
** On-Chip VGA Setting**
On-Chip VGA
On-Chip Frame Buffer size [Disabled]
[By SPD]
[1.5]
[7]
[3]
[3]
[Enabled]
[Auto]
[Enabled]
[Enabled]
[Disabled]
[Enabled]
[16 Min]
[64]
[Enabled]
[8MB]
# $ %
Move Enter: /-/PU/PD: Value F10: Save Esc: Exit F1: General Help
F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
Spread Spectrum: When the system clock generator pulses, the extreme values of the pulse generate
excess EMI. Enabling pulse spectrum spread modulation changes the extreme values from spikes to flat
curves, thus reducing EMI. This benefit may in some cases be outweighed by problems with timing-critical
devices, such as a clock-sensitive SCSI device.
DRAM Timing Selectable: This item allows you to select the value in this field, depending on whether the
board has paged DRAMs or EDO (extended data output) DRAMs.
CAS Latency Time:
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.
Active to Precharge Delay: In the BIOS tRAS is often called something like Active to Precharge, and can
usually be set to 5T, 6T, or 7T. tRAS is the minimum bank active time from active to precharge of same bank,
not that probably means much to most people.