Lanner electronics EM-9560 Series, Руководство пользователя, Страница: 37 / 54

Chapter 3 BIOS Setup
3.5 Advanced Chipset Features Setup
When you select the “CHIPSET FEATURES SETUP” on the main program, the screen display will appears as:
Chipset Features Setup Screen
Phoenix - Award BIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
Menu Level
f
X
DRAM Timing By SPD
DRAM Clock
SDRAM Cycle Length
Bank Interleave
Memory Hole
P2C/C2P Concurrency
System BIOS Cacheable
Video RAM Cacheable
Frame Butter Size
AGP Aperture Size
AGP-4X Mode
AGP Driving Control
AGP Driving Value
Panel Type
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
PCI Delay Transaction
PCI#2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read [Disabled]
[HCLK+33M]
[3]
[Disabled]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
[8M]
[64M]
[Enabled]
[Auto]
[DA]
[800
°
600 TFT (LVDS)]
[Enabled]
[Enabled]
[Enabled]
[Disabled]
[Enabled]
[Disabled]
[Disabled]
³
Move Enter: Select +/-/PU/PD: Value F10: Save Esc: Exit F1: General Help
F5: Previous Values F7: Optimized Defaults
Spread Spectrum: When the system clock generator pulses, the extreme values of the pulse generate
excess EMI. Enabling pulse spectrum spread modulation changes the extreme values from spikes to flat
curves, thus reducing EMI. This benefit may in some cases be outweighed by problems with timing-critical
devices, such as a clock-sensitive SCSI device.
Onboard Lan Boot ROM:
Unless you intend to boot using PXE Enabled/Disabled.
DRAM Timing By SPD: This item allows you to select the value in this field, depending on whether the
board has paged DRAMs or EDO (extended data output) DRAMs.
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User’s Manual