BL600-Sx Hardware Integration Guide
Single Mode BLE Module
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CONN-HIG-BL600
Two-way hardware flow control is implemented by UART_RTS and UART_CTS. UART_RTS is an output and
UART_CTS is an input. Both are active low.
These signals operate according to normal industry convention. UART_RX, UART_TX, UART_CTS, UART_RTS
are all 3.3 V level logic (tracks VCC). For example, when RX and TX are idle they sit at 3.3 V. Conversely for
handshaking pins CTS, RTS at 0 V is treated as an assertion.
The module communicates with the customer application using the following signals:
Port /TXD of the application sends data to the module’s UART_RX signal line
Port /RXD of the application receives data from the module’s UART_TX signal line
Note:
The BL600 serial module output is at 3.3V CMOS logic levels (tracks VCC). Level conversion must
be added to interface with an RS-232 level compliant interface.
Some serial implementations link CTS and RTS to remove the need for handshaking. Laird does not
recommend linking CTS and RTS other than for testing and prototyping. If these pins are linked and the host
sends data at the point that the BL600 deasserts its RTS signal, then there is significant risk that internal
receive buffers will overflow, which could lead to an internal processor crash. This will drop the connection
and may require a power cycle to reset the module. Laird recommends that the correct CTS/RTS handshaking
protocol be adhered to for proper operation.
Table 14: UART Interface
Signal Name
Pin No I/O
Comments
SIO_21 / UART_TX
32
O
SIO_21 (alternative function UART_TX) is an output, set high (in FW).
SIO_22 / UART_RX
33
I
SIO_22 (alternative function UART_RX) is an input, set with internal
pull-up (in FW).
SIO_23 / UART_RTS 34
O
SIO_23 (alternative function UART_RTS) is an output, set low (in FW).
SIO_24 / UART_CTS 35
I
SIO_24 (alternative function UART_CTS) is an input, set with internal
pull-down (in FW).
The UART interface is also used to load customer developed
smart
BASIC application script.
BL600-Sx-04 module HW has an improved UART with a deep buffer (increased the UART_RX receive buffer
from 2 bytes to 6bytes).
5.6
SPI Bus
The SPI interface is an alternate function on SIO pins, configurable by
smart
BASIC.
The Module is a master device that uses terminals SPI_MOSI, SPI_MISO, and SPI_CLK. SPI_CSB is implemented
using any spare SIO digital output pins to allow for multi-dropping.
The SPI interface enables full duplex synchronous communication between devices. It supports a 3-wire
(SPI_MOSI, SPI_MISO, SPI_SCK,) bidirectional bus with fast data transfers to and from multiple slaves.
Individual chip select signals will be necessary for each of the slave devices attached to a bus, but control of
these is left to the application through use of SIO signals. I/O data is double buffered.
BL600
UART_TX
UART_RX
UART_CTS
UART_RTS
Application - Host
/RXD
/TXD
/RTS
/CTS
