37
4.2: L-502 connectors description.
Table 4-2: Internal signal connector
Signal
name
Comm
on
point
Direc-
tion
State after
connection
Description
DI<16…1>
DGND
Input
Input
16-bit digital input, where
DI1 is the low bit, DI16 is the high bit of the 16-bit
word. It is possible to programmatically turn the 2.2
kOhm pull-up resistors to a high logic level
independently on the lines of the low and high byte. The
DI_SYN2 input does not bypass the external TTL source
even when the power is off.
DO<16…1>
DGND
Output
Z-state
16-bit digital output, where
DO16 – high bit, DO1 – low bit of the 16-bit word.
Lines DO1 ... DO8 refer to the low byte, and lines DO9
... DO16 - to the high one. Program control Z- state is
independent for the high and low bytes. It is possible to
force the active state of the outputs of each byte when
the power is turned on by installing jumper, section
DGND
—
—
—
A common-wire circuit for digital inputs and outputs.
DI_SYN2
DGND
Input-
output
Input
Sync input 2, which can also act as an additional input to
the digital input. Compatible with the output logic level
of TTL/CMOS- cells with a supply voltage of +2.5 V to
+5 V. The input has an extended range of maximum
permissible voltages (± 10 V relative to GND).
Especially does not specify the minimum rate of
increase of the signal drop at the input DI_SYN2, since
there is a Schmitt trigger on this input. There is a
software option to turn the 1k pull-up resistor to a high
logic level at this input. DI inputs do not bypass the
external TTL source even when the power is off.
+3.3 V
DGND
Output
3.3
V
3.3 V supply external digital nodes.
Attention! In versions 1 and 2 of L-502 (serial numbers
start with the digit "1" or "2"), the short circuit of the +
3.3V output is inadmissible (it leads to failure of the
L-502!
In version 3, a short circuit of +3.3 V is permissible.
For the maximum permissible voltages and currents at the contacts of the connectors, see the
, on p.
