26
The device and principle of operation L-502.
The secondary synchronization circuit (
II
)
is the ADC data selection circuit depending on
the secondary synchronization conditions, operating exclusively against the background of the
previously started clock signal from the output of the primary synchronization circuit (
I
), i.e.
against the background of the started data stream of the ADC.
The following ADC data resolution synchronization modes are supported:
•
No synchronization (transparency mode)
•
Synchronization from an analog signal in the selected ADC channel
•
Digital synchronization with the selected signal from the inputs DI1 ... DI16, or
DI_SYN1, or DI_SYN2
The following modes of sensitivity to the fluctuations of the synchronization signal are
supported:
•
Enable of ADC data
on the edge (drop)
of an analog or digital signal
•
Enable of ADC data at
a level
"above the threshold" or "below the threshold" (for
analog synchronization) or
at the logic level
"1" (for digital synchronization)
The following ADC data inhibit modes are supported:
•
Software prohibition (stop) with the possibility of re-authorization (if the previously
set enable condition is repeated) without restarting the primary synchronization
scheme
•
Automatic prohibition (stop) after entering the specified number of frames (from 1 to
2
32
-1 frames) with the possibility of re-authorization (if the previously set resolution
condition is repeated) without restarting the primary synchronization scheme
3.3.6. Setting the ratio between the time of setting the signal and the resolution
for each channel of the ADC is a unique possibility of the L-502!
Above was the principle of the frame-by-line input of ADC data, which was applied in all L-
CARD ADCs with the input channel switch, up to synchronization frequency, frame size and
interframe delay. But with L-502 this principle is developed for better adaptation to the output
physical properties of the signal source. Further we will discuss it more precisely.
If L-502 is used at the highest possible data acquisition frequency from each channel, then set
n
sw
= 1, which means that the sampling period of one measurement channel is
t
sw
=
t
ref
, during
which only one ADC sample is converted. For example, for
f
ref
=2 MHz time
t
sw
=
t
ref
= 0,5 μs is a
fairly short switching period of the channel switch, which imposes restrictions on the output
impedance of the signal source (and the wires from it): the impedance should be sufficiently small
(not more than 50 Ohm) and not have a large reactive component, so that the duration of the
transient process caused by circuit switching does not exceed 0.5 μs. In other words, the signal
source should be no more than 50 Ohm and have a short or coordinated cable. For those who used
the L-783, these requirements and these conditions of use roughly correspond to the conditions of
application of the L-783 in the multichannel mode with the maximum ADC conversion frequency
of the 3 MHz, but with the difference that the L-502 ADC's resolution is 16 bits, not 12, and the
electronic switch in L-502 is much more "quiet" (i.e. it injects a significantly smaller parasitic
charge into the signal chain at the time of commutation, and therefore causes a significantly smaller
shock excitation for a possible transient process in the signal circuit).
But if you want to use L-502 at a data acquisition rate for each channel less than the
maximum, and you can reduce the switching frequency, then in L-502 with internal synchronization
there is no reduction in the frequency of ADC startup, and
n
sw
> 1 is set, for example, as it is shown
. But, in the sense of
n
sw
– this is the number of cycles of ADC conversion for one
