23
3.3: Operation principle
where
f
ref
can be 2.0 or 1.5 MHz for an internal synchronization or ≤2.0 MHz for an external,
n
к
= {1,2,…, 256},
n
sw
={1,2,…,2097152},
n
d
={0,1,…,2097151}.
The above-mentioned frame structure of the ADC data is shown in
. Here, for
example, a 3-channel ADC mode operation (
n
к
= 3) is taken with a non-zero interframe delay
t
d
.
2
1
3
2
3
Канал 1
Канал 2
Канал 3
t
k
n
k
=3
t
d
t
k
t
ch
Кадр
Межкадровая
задержка
Кадр
Межкадровая
задержка
t
sw
1
Момент сэмплирования отсчётов данных АЦП
Номер
логического
канала АЦП
Fig. 3-1. Illustration of the personnel principle for acquiring ADC data
3.3.3. Digital input channel.
Synchronous digital input occurs with a period of
t
ref
*
n
din
,
where
n
din
={1,2,…,2097152} is a configurable frequency division factor for synchronous
digital input
3.3.4. Digital output and DAC channels
Synchronous digital output, as well as updating both channels of the DAC, occurs with a
period of 2*
t
ref
. If the data buffer for the output and the DAC is empty, then the last value is held at
the outputs.
Channel 1
Channel 2
Channel 3
ADC logical
channel
number
Frame
Frame
Interframe
delay
Interframe
delay
Sampling time of ADC samples
