VITA 57 Development Kit User's Guide
Troubleshooting
Page 14
SD.DT.F79-0e
4.5
Low Level Debug with IO Command
This command can be used to read/write FPGA registers. First, get the FPGA registers physical base address
using "lspci -x":
0000:04:00.0 Memory controller: Teknor Industrial Computers Inc Unknown device
9050 (rev fe)
00: 59 10 50 90 06 00 10 00 fe 00 80 05 08 00 00 00
10: 04 00 00 80 00 00 00 00 00 08 00 80 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 59 10 01 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 42 01 00 00
The 32bit swapped address is stored in BAR2 at PCI configuration offset 0x18. In the example above, the
address is: swap32(0x00080080) = 0x80000800
The examples below assume that FPGA registers are mapped at this address in physical memory.
When reading or writing 32bit data using "IO", the data has to be swapped. This does not apply to the
adress parameter; only to data.
Here is an example with TX1, TX2, RX1 and RX2 using a loopback connector on the FMC-SER0 front panel.
Set VADJ to 3V3 in "REGI0 general purpose" register at offset 0x380 (if not yet done) :
[root@localhost ~]# io
−
4
−
w 0x80000b80 0x08000000
[root@localhost ~]# io
−
4
−
r
−
l 0x4 0x80000b80
80000b80: 08000000
Set signals controlling buffer output enable as outputs by setting channel 8 "GPIO control" register at offset
0x200 :
[root@localhost ~]# io
−
4
−
w 0x80000a00 0x03000000
[root@localhost ~]# io
−
4
−
r
−
l 0x4 0x80000a00
80000a00: 03000000
Set signals controling TX1 and TX2 as outputs by setting channel 0 "GPIO control" register at offset 0x000
[root@localhost ~]# io
−
4
−
w 0x80000800 0x0a000000
[root@localhost ~]# io
−
4
−
r
−
l 0x4 0x80000800
80000800: 0a000000
Enable output of buffers by setting channel 8 "GPIO DataOut" register at offset 0x204:
[root@localhost ~]# io
−
4
−
w 0x80000a04 0x01000000
[root@localhost ~]# io
−
4
−
r
−
l 0x4 0x80000a04
80000a04: 01000000
If FMC-SER0 is configured for RS422/485:
Set TX1 to 1 by setting channel 0 ”GPIO DataOut” register at offset 0x004
−
>
should reread TX1 = 1, but also RX1 = 1 because of loopback, in channel 0
”GPIO DataIn” register at offset 0x008
[root@localhost ~]# io
−
4
−
w 0x80000804 0x08000000
[root@localhost ~]# io
−
4
−
r
−
l 0x4 0x80000808
80000808: 09000000
