Keysight M8121A, Руководство пользователя

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Keysight M8121A Arbitrary Waveform Generator User Guide 133
Remote Programming 6
:CALibrate:LATency[:STEP] ARM | ADJust | STOP
Command :CALibrate:LATency ARM | ADJust | STOP
Parameters STOP: default value
ARM: Arms the deterministic latency mechanism. Must be sent before the
source (i.e. M8131A) sends sync pulses or ODI data
ADJust: Performs deterministic latency adjustment procedure. Requires
ARM to have been previously sent, and expects that the source (i.e.
M8131A) is in appropriate mode before this command is sent.
Parameter Suffix None
Description This command executes a step in the latency calibration of the data path
between M8131A digitizer (master) and M8121A AWG (slave). In a 2
channel AWG, affects both channels if enabled. If both channels can be
successfully calibrated, then they will be adjusted to ensure that they use
the same latency i.e. :CALibrate:LATency:VALue applies to both channels.
The status of each channel can be checked using
:CALibrate:LATency:STATus{1|2}?
Examples :CAL:LAT ARM
:CALibrate:LATency:VALue
Command :CALibrate:LATency:VALue <value> | MINimum | MAXimum
Query :CALibrate:LATency:VALue?
Parameter <value> | MINimum | MAXimum
Description Use :CALibrate:LATency:VALue? to query the current value of
Deterministic Latency in seconds. This value is set during the Deterministic
Latency ADJustment phase, and maybe subsequently modified by the
user.
A value of 9.91E37 indicates that deterministic latency adjustment has
either not yet been performed, has failed to complete, or has become
invalid. Since :CALibrate:LATency[:STEP] ADJust acts on both channels,
and sets the latency to the same value for both channels, the value
returned by :CALibrate:LATency:VALue? is the same for both channels.
After Deterministic Latency Calibration has been successfully run, the
range can be queried using CALibrate:LATency:VALue? MINimum |
MAXimum. The results from this query are only valid if
CALibrate:LATency:VALue? is not 9.91E37. The MINimum value is the
value determined during the Deterministic Latency ADJustment phase.