1 Theory of Operation: M31/M33XX Digitizers
1. 3 Clock System
The M31/M33XXA Digitizers uses an internally generated high-quality clock (CLKref) which is
phase-locked to the chassis clock. Therefore, this clock is an extremely jitter-cleaned copy of the
chassis clock. This implementation achieves a jitter and phase noise above 100 Hz which is
independent of the chassis clock, depending on it only for the frequency absolute precision and
long term stability. A copy of CLKref is available at the CLK connector (Table 13).
CLKref is used as a reference to generate CLKsys, the high-frequency clock used to sample data.
Advanced
: Chassis Clock Replacement for High-Precision
Applications: For applications where clock stability and precision
is crucial (e.g. GPS, experimental physics, etc.), the user can
replace the chassis clock with an external reference. In the case
of PXI/PXIe, this is possible via a chassis clock input connector or
with a PXI/PXIe timing module. These options are not available in
all chassis, please check the corresponding chassis specifications.
CLK Output Options
Programming Definitions
Option
Description
Name
Value
Disable
The CLK connector is disable
n/a
0 (default)
CLKref Output A copy of the reference clock is available at the CLK connector n/a
1
Table 13: M31/M33XXA Digitizers output clock configuration
1. 3. 1 FlexCLK Technology (models with variable sampling rate)
The sampling frequency of the M31/M33XXA Digitizers (CLKsys frequency) can be changed using
the advanced clocking system shown in Figure 7.
16
Keysight M31XXA/M33XXA Digitizer User's Guide
Содержание M31 A Series
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