1 Theory of Operation: M31/M33XX Digitizers
Keysight M31XXA/M33XXA Digitizer User's Guide
17
Figure 7: Functional diagram of the M31/M33XXA Digitizers FlexCLK system
where:
CLKref is the internal reference clock, which is phase-locked to the chassis
clock.
CLKsys is the system clock, used to sample data.
CLKsync is an internal clock used for the synchronization features of the
M31/M33XXA Digitizers.
PXI CLK10 is the 10 MHz clock of the PXI/PXIe backplane (PXI/PXIe only).
The CLKsys frequency can be changed within the range indicated in the datasheet of the
corresponding product (function clockSet- Frequency, Section 2.3.4.17 on page 44). The CLKsync
frequency changes with the CLKsys frequency as follows:
The CLKsync frequency is returned by the function
CLK Set Frequency Mode
Programming Definitions
Option
Description
Name
Value
Low Jitter Mode The clock system is set to achieve the lowest jitter,
sacrificing tuning speed
CLK_LOW_JITTER
0
Fast Tuning
Mode
The clock system is set to achieve the lowest tuning time,
sacrificing jitter performance
CLK_FAST_TUNE
1
Table 14: Clock set frequency mode (function
Содержание M31 A Series
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