KDC-MP6090R/MP7018/MP8017
10
CIRCUIT DESCRIPTION (MP3)
MP3 DSP IC : STA013 (X32-5080 : IC5)
■
OUT SIDE VIEW
●
SINGLE CHIP MPEG2 LAYER 3 DECODER SUP-
PORTING.
Note
(Z919 is guaranteed to the MPEG 1.0 Layer
3
.)
•
All features specified for Layer in ISO/IEC11172-3
(MPEG 1 Audio)
•
All features specified for Layer
3
in ISO/IEC13818-3.2
(MPEG 2 Audio)
•
Lower sampling frequencies syntax extension, (not spec-
ified by ISO) called MPEG2.5
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DECODES LAYER III STEREO CHANNELS, DUAL
CHANNEL, SINGLE CHANNEL (MONO)
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SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FRE-
QUENCIES AND THE EXTENSION TO MPEG 2.5: 48,
44.1, 32, 24, 22.05, 16, 12, 11.025, 8kHz
●
ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COM-
PRESSED BIT STREAM WITH DATA RATE FROM 8
Kbit/s UP TO 320 Kbit/s
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DIGITAL VOLUME CONTROL
●
DIGITAL BASS & TREBLE CONTROL
●
SERIAL BITSTREAM INPUT INTERFACE
●
ANCILLARY DATA EXTRACTION VIA I
2
C INTERFACE
●
SERIAL PCM OUTPUT INTERFACE (I
2
C AND OTHER
FORMATS)
●
PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM
CLOCK GENERATION
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LOW POWER CONSUMPTION: 85mW AT 2.4V
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CRC CHECK AND SYNCHRONISATION ERROR
DETECTION WITH SOFTWARE INDICATORS
●
I2C CONTROL BUS
●
LOW POWER 3.3V CMOS TECHNOLOGY
●
10MHz,14.31818 MHz, OR 14.7456MHz EXTERNAL
INPUT CLOCK OR BUILT-IN INDUSTRY STANDARD
XTAL OSCILLATOR DIFFERENT FREQUENCIES MAY
BE SUPPORTED UPON REQUEST TO STM
Note
EXTERNAL CLOCK: 10MHz
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APPLICATIONS
●
PC SOUND CARDS
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MULTIMEDIA PLAYERS
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DESCRIPTION
The STA013 is a fully integrated high flexibility MPEG Layer
III Audio Decoder, capable of decoding Layer
3
com-
pressed elementary streams, as specified in MPEG 1 and
MPEG 2 ISO standards.The device decoders also elemen-
tary streams compressed by using low sampling rates, as
specified by MPEG 2.5.
STA013 receives the input data through a Serial Input
Interface.The decoded signal is a stereo,mono, or dual
channel digital output that can be sent directly to a D/A con-
verter, by the PCM Output Interface.This interface is soft-
ware programmable to adapt the STA013 digital output to
the most common DACs architectures used on the market.
The functional STA013 chip partitioning is described in Fig. 1.
I
2
C CONTROL
SERIAL
INPUT
INTERFACE
BUFFER
PARSER
MPEG 2.5
LAYER
III
DECODER
CORE
CHANNEL
CONFIG.&
VOLUME
CONTROL
OUTPUT
BUFFER
PCM
OUTPUT
INTERFACE
10
11
9
5
26
8
28
21
20
12
24
25
3
4
6
7
SYSTEM & AUDIO CLOCKS
TEST INTERFACE
RESET
SDA
SCL
SDI
SCKR
BIT_EN
SRC INT
OUT_CLK/
DATA_REQ
XTI
XTO OCLK
TESTEN SCANEN
SDO
SCKT
LRCKT
Fig. 1 Block diagram: MPEG 2.5 Layer
#
Decoder hardware Partitioning