
DV-203/2070/DVF-5010/9010/K7010
CIRCUIT DESCRIPTION
20
Pin No. Pin Name
I/O
Descriptions
1
MUTE
I
Mute(H:on)
2
BCK
I
BCK input port
3
DATA
I
Data input port
4
LRCK
I
LRCK input port
5
RST
I
Reset input port(L:reset)
6
VSS
-
GND
7
IBF
I
Input format setting(1)
8
IIS
I
Input format setting(2)
9
IUD
I
Inverted input port of LRCK
10
IW0
I
Input data period setting(1)
11
IW1
I
Input data period setting(2)
12
VSS
-
GND
13-16
NCON3-0
O
Test port
17
VDD
-
Power supply port
18
DR0N0
I
ROM compensation on/off
19
DR0N1
I
Filter compensation on/off
20
NT
I
Connect H level
21
RND0
I
Open
22
RND1
I
Open
23
OBF
I
Output format setting(1)
Pin No. Pin Name
I/O
Descriptions
24
OIS
I
Output format setting(2)
25
OLRRL
I
Output change port
26
OUD
I
Edge setting of LRCK0
27
FILN
I
Connect H level
28
VSS
-
GND
29
LRCKO
O
LRCK output port
30
DATAO
O
DATA output port
31
BCKO
O
BCK output port
32
DRVW
I
Connect H level
33
THRMN
I
Through mode
34
ICTH
I
Phase setting of internal
oscillation
35
VDD
-
Power supply port
36
CK
I
Master clock input port
37
X0
O
Crystal output port
38
VSS
-
GND
39
VDD
-
Power supply port
40,41
MCK0,1
O
Master clock output port
42
VSS
-
GND
43,44
MMOD0,1
I
Master clock frequency setting
7-2 Block diagram
7. DSP/D.R.I.V.E.
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: KAN06 (X32 : IC2)
7-1 Pin description
S/P
DELAY
SEL
FILTER1
Data
correction
P/S
LRCK0
BCK0
DATA0
FILTER2
differential
amp
differential
amp
Data detection
L. P. F.
CLOCK Gen.
LRCK
DRON1
FILN
MMOD0
MMOD1
ICTH
CK
X0
MCK0
MCK1
DRON0
THRMN
DV-203/DVF-5010(K)
COVER1,1(
98.12.11
14:23
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