Kenwood DV-203, Руководство по обслуживанию, Страница: 18 / 58

DV-203/2070/DVF-5010/9010/K7010
CIRCUIT DESCRIPTION
19
Pin No. Pin Name I/O Descriptions
1 DGND I Digital GND.
2 MCLK I Master clock input. Connect to an external clock source at either 256,384 or 512Fs.
3 CLATCH I Latch input for control data. This input is rising edge sensitive.
4 CCLK I
Control clock input for control data. Control input data must be valid on the rising edge of CCLK.
CCLK may be continuos or gated.
5 CDATA I
Serial control input, MSB first, containing 16 bits of unsigned data per channel.
Used for specifying channel specific attenuation and mute.
Select the master clock mode as either 384 times the intended sampling frequency(HI) or 256
6 384/256 I
times the intended sampling frequency(LO). The state of this input should be hardwired to logic
HI or logic LO or may be changed while the AD1855 is in power down/reset.
It must not be changed while the AD1855 is operational.
7 X2MCLK I Select internal clock doubler(LO) or internal clock =MCLK(HI).
8 ZEROR O
Right channel zero flag output. This port goes HI when left channel has no signal input
for more than 1024 LR clock cycles.
Deemphasis. Digital deemphasis is enabled when this input signal is HI. This is used to impose
9 DEEMP I a 50/15 ms response characteristic on the output audio spectrum at an assumed 44.1kHz
sample rate.
10 48/96 I Selects 48kHz(LO) or 96kHz sampling frequency control.
11 AGND I Analog GND
12 OUTR+ O Right channel positive line level analog output
13 OUTR- O Right channel negative line level analog output
14 FILTER O
Voltage reference filter capacitor connection. Bypass and decouple the voltage reference
with parallel 10uF and 0.1uF capacitor to the AGND.
15 AGND I Analog GND
16 OUTL- O Left channel negative line level analog output
17 OUTL+ O Left channel positive line level analog output
18 AVDD I Analog power supply. Connect to the 5V supply.
19 FILTB - Filter capacitor connection, connect 10uF capacitor to AGND.
20 IDPM1 I Input serial data port mode control one. With IDPM0, defines 1 of 4 serial modes.
21 IDPM0 I Input serial data port mode control zero. With IDPM1, defines 1 of 4 serial modes.
22 ZEROL O
Left channel zero flag output. This port goes HI when right channel has no signal input
for more than 1024 LR clock cycles.
23 MUTE I Mute. Assert HI to mute both stereo analog outputs. Dessert LO for normal operation.
Power down/reset. The AD1855 is placed in a low power consumption mode when this port is
24 PD/RST I held LO. The AD1855 is reset on the rising edge of this signal. The serial control port registers
are reset to the default values. Connect HI for normal operation.
25 LRCLK I Left/right clock input for input data. Must run continuously.
26 BCLK I Bit clock input for input data. Need not run continuously;may be gated or used in a burst fashion.
27 DSDAT I
Serial input, MSB first, containing two channels of 16/18/20/24 bits of twos compliment data
per channel.
28 DVDD I Digital power supply. Connect to the d5V supply.
IDPM1 (PIN20) IDPM0 (PIN21) Serial data input format
0 0 Right-Justified (16 bits only)
0 1 I2S Compatible
1 0 Left-Justified
1 1 DSP
6-2 SERIAL DATA INPUT MODE
6. DAC : AD1855 (X32: IC3, 4)
6-1 Pin description
DV-203/DVF-5010(K) COVER1,1( 98.12.11 14:22 y [ W 32
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