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Kaya Instruments KY-FGK Скачать руководство пользователя страница 24

Komodo CXP Reference Guide

23

SODIMM DDR3

DDR3 IP

(Slave)

on-board DDR3

DDR3 IP

(Master)

RZQ

sharing

enabled

RZQ

SODIMM DDR3

DDR3 IP

(Master)

on-board DDR3

DDR3 IP

(Slave)

sharing

enabled

Figure 11: RZQ connection when both memories are used

4.10.1

On-Board 16Gb DDR3

The

Komodo CXP

supports four, 32Mx16x8 bank, DDR3 SDRAM interface for very high-speed

sequential memory access. The 64-bit data bus consists of four x16 devices with a single address or

command bus. This interface support rates of up to 1066 MT/s. This interface connects to the

vertical I/O banks on the top edge of the FPGA.

Board Components

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Содержание KY-FGK

Страница 1: ...Reference Guide Part No KY FGK July 2018 20 aMesila St Nesher 3688520 Israel P O B 2 5 0 0 4 H a i f a 3 1 2 5 0 0 1 I s r a e l Tel 972 72 2723500 Fax 972 72 2723511 w w w k a y a i n s t r u m e n...

Страница 2: ...do CXP Board components 12 4 5 Featured device Arria V GZ FPGA 12 4 6 FPGA Configuration 12 4 6 1 FPGA configuration via JTAG 13 4 6 2 FPGA configuration via on board flash memory 13 4 7 Clocking 14 4...

Страница 3: ...ratings for GPIO 40 Available Configurations 41 Available Configurations 41 Top Level Example Design 42 Reference Design 43 9 1 Functional block diagram 43 9 1 1 DDR3 memories 44 9 1 2 PCI Express 44...

Страница 4: ...IGURE 16 FAN CONNECTIONS 35 FIGURE 17 PCB MECHANICAL DIMENSIONS 36 FIGURE 18 FUNCTION DIAGRAM 43 FIGURE 19 DDR3 SODIMM 46 FIGURE 20 KOMODO CXP WITH JTAG CONNECTION 47 Tables TABLE 1 KOMODO CXP BOARD C...

Страница 5: ...IVER OUTPUTS 38 TABLE 17 LVDS INPUT DC SPECIFICATIONS RECEIVER INPUTS 39 TABLE 18 LVTTL INPUT SPECIFICATIONS 39 TABLE 19 LVTTL OUTPUT SPECIFICATIONS 39 TABLE 20 TTL INPUT SPECIFICATIONS 39 TABLE 21 TT...

Страница 6: ...e product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooli...

Страница 7: ...ay be damaged Disclaimer Even if the product is used properly KAYA Instruments assumes no responsibility for any damages caused by the following Earthquake thunder natural disaster or fire resulting f...

Страница 8: ...rnal devices The Komodo CXP uses standard DIN connectors as a CoaXPress interface to the camera and standard 100 mil headers for general purpose I O All of these features combine make the Komodo CXP i...

Страница 9: ...n security Temperature control Fan control 4 general purpose indication LEDs and 8 CoaXPress dedicated LEDs 0 C to 50 C operating environment temperature Product Applications Machine Vision Networking...

Страница 10: ...CXP Reference Guide 9 Ordering Codes 4 0 0 0 8 0 8 0 16 Gb 1 48 Gb 2 80 Gb 3 144Gb KY FGK Notes 1 Maximum of Receiver and Transmitter channels together is 8 2 Custom models available on request Key Fe...

Страница 11: ...mory Clocking circuitry 125 MHz LVDS oscillator for transceiver reference clock 100 MHz reference clock from the PCIe edge connector 25 MHz single ended oscillator for DDR3 memory Memory 16Gb DDR3 64...

Страница 12: ...qualizer Driver 1 Equalizer Driver 8 Figure 1 Board block diagram External View of the Board Up to 128Gb SODIMM Connector J11 User LEDs D1 D4 16 Gb SDRAM U14 U18 U22 U26 Power Connector J5 GPIO J2 125...

Страница 13: ...4 SODIMM memory Up to 128Gb DDR3 SODIMM with 64 bit data bus General User Input Output D1 D4 User LEDs Four user LEDs Active low Communication Ports J17 PCIe edge connector Gold plated edge fingers co...

Страница 14: ...JTAG header J3 Figure 3 JTAG connector 4 6 2 FPGA configuration via on board flash memory The Komodo CXP has an on board EPCQ256 flash memory Upon the power up the FPGA tries to fetch the configurati...

Страница 15: ...n Figure 5 Clocks pin assignments signal name and functions Board reference Signal Name Arria V GZ Pin Number Arria V GZ Clock Name I O Standard Description U2 cxp_clkp W6 REFCLK0Rp LVDS 125 MHz osci...

Страница 16: ...he Arria V GZ FPGA The following figure describes what each bank is used for 7A 7B 7C 7D 7E 8E 8D 8C 8B 8A 4A 4B 4C 4E 4D 3D 3E 3C 3B 3A B2R B0R B1R B2L B0L B1L CoaXPress transceirers PCIe_Tx PCIe_Rx...

Страница 17: ...eference Guide 16 4 8 1 General purpose I O The Komodo CXP supports 40 different I O connections on the FPGA as described in the figure and table below Figure 7 General purpose Inputs and outputs Boar...

Страница 18: ...nal of this LVDS The differential pair is converted to a single output on the FPGA 8 9 io_out 0 AF26 3 3 V LVTTL Optically isolated outputs 10 io_out 1 AE26 3 3 V LVTTL Optically isolated outputs 11 i...

Страница 19: ...nal of this LVDS The differential pair is converted to a single output on the FPGA 8 9 io_out 4 AF25 3 3 V LVTTL Optically isolated outputs 10 io_out 5 AE25 3 3 V LVTTL Optically isolated outputs 11 i...

Страница 20: ...nal also enables data transfer from pins AL26 and AM25 on the FPGA to pins 5 8 on the GPIO header 4 8 2 General purpose LEDs On the Komodo CXP there are four user define LEDs all are green light and a...

Страница 21: ...nnected to the FPGA Board reference J17 Signal Name Arria V GZ Pin Number I O Standard Description A1 pcie_prsntn1n 3 3 V LVTTL Hot plug presence detect B17 pcie_prsntn1n_x1 3 3 V LVTTL Hot plug prese...

Страница 22: ...PCML B41 pcie_rx_p 6 U33 1 5 V PCML B42 pcie_rx_n 6 U34 1 5 V PCML B45 pcie_rx_p 7 R33 1 5 V PCML B46 pcie_rx_n 7 R34 1 5 V PCML Table 6 PCIe pin assignments signal name and functions Memory On the Ko...

Страница 23: ...ed the RZQ signal must be connected to both of the DDR3 controller Both controllers must have sharing enabled One controller must be configured as master this is done by selecting Master in the PHY Se...

Страница 24: ...ection when both memories are used 4 10 1On Board 16Gb DDR3 The Komodo CXP supports four 32Mx16x8 bank DDR3 SDRAM interface for very high speed sequential memory access The 64 bit data bus consists of...

Страница 25: ...Standard Description Common control signals to all four on board SDRAMs N3 ddr3_2_a 0 AC14 1 35 V SSTL Address bus P7 ddr3_2_a 1 AD15 1 35 V SSTL P3 ddr3_2_a 2 W21 1 35 V SSTL N2 ddr3_2_a 3 AG12 1 35...

Страница 26: ...TL A7 ddr3_2_dq 39 AN15 1 35 V SSTL H3 ddr3_2_dq 56 AD16 1 35 V SSTL F2 ddr3_2_dq 57 W15 1 35 V SSTL G2 ddr3_2_dq 58 W16 1 35 V SSTL F7 ddr3_2_dq 59 AG16 1 35 V SSTL H8 ddr3_2_dq 60 W17 1 35 V SSTL F8...

Страница 27: ...2_dq 7 AH23 1 35 V SSTL G2 ddr3_2_dq 24 AF18 1 35 V SSTL H8 ddr3_2_dq 25 W18 1 35 V SSTL E3 ddr3_2_dq 26 AF19 1 35 V SSTL F2 ddr3_2_dq 27 AG18 1 35 V SSTL F7 ddr3_2_dq 28 AA18 1 35 V SSTL H7 ddr3_2_dq...

Страница 28: ...a single address or command bus This interface support rates of up to 1066 MT s This interface connects to the vertical I O banks on the top edge of the FPGA Board reference J11 Signal Name Arria V GZ...

Страница 29: ...3 ddr3_1_dm 6 D22 1 35 V SSTL Write mask byte 6 136 ddr3_1_dm 7 F27 1 35 V SSTL Write mask byte 7 177 ddr3_1_dq 0 J27 1 35 V SSTL Data bus 163 ddr3_1_dq 1 L27 1 35 V SSTL 176 ddr3_1_dq 2 M27 1 35 V SS...

Страница 30: ...141 ddr3_1_dq 56 E26 1 35 V SSTL 143 ddr3_1_dq 57 F26 1 35 V SSTL 129 ddr3_1_dq 58 H28 1 35 V SSTL 142 ddr3_1_dq 59 E28 1 35 V SSTL 132 ddr3_1_dq 60 G24 1 35 V SSTL 140 ddr3_1_dq 61 H29 1 35 V SSTL 13...

Страница 31: ...onnector lf 0 AC6 3 3 V LVTTL Low speed data out cxp_on 0 AN7 2 5V PoCXP enable active low pwrg 0 AN24 3 3 V LVTTL If PoCXP is enabled this signal indicates that the output voltage has reached 90 of t...

Страница 32: ...If PoCXP is enabled this signal indicates that the output voltage has reached 90 of the full 24V cxp_flagb 4 T23 3 3 V LVTTL If PoCXP is enabled this signal indicates current limit or under voltage or...

Страница 33: ...ed this signal indicates current limit or under voltage or over temperature state of the over current protection load switch SDOp 7 AL2 1 5V PCML High Speed Data In positive AL1 1 5V PCML High Speed D...

Страница 34: ...ibes the Rx connection of the equalizer to the DIN connector Figure 13 Rx channel connection to the equalizer The following figure describes the Tx connection of the driver to the DIN connector Figure...

Страница 35: ...e LED off led_r 0 AA9 2 5 V Open drain D2 led_g 1 AF10 2 5 V Open drain led_r 1 AB9 2 5 V Open drain D3 led_g 2 AG10 2 5 V Open drain led_r 2 AG9 2 5 V Open drain D4 led_g 3 AH10 2 5 V Open drain led_...

Страница 36: ...rt turns the FAN on driving logic 0 on the I O turns the FAN off 3 fan_tacho AF24 3 3 V LVTTL Fan s tacho output used for measuring the rotation speed of the fan Table 11 Fan pin assignments signal na...

Страница 37: ...mechanical dimensions are as defined in Figure 17 For more detailed information please contact KAYA Instruments representative Figure 17 PCB Mechanical Dimensions Absolute maximum ratings Specificatio...

Страница 38: ...e power sources as stated in the following table see PCIe gen 3 0 specifications for more information Power Source Voltage V Current A Maximum Wattage W External power connector 12 4 34 104 25 W PCI E...

Страница 39: ...istics for board IO s Symbol Parameter Condition Pin MIN Typ MAX Units VOD Differential Output Voltage RL 100 DOUT DOUT 250 350 450 mV VOD Change in Magnitude of VOD for Complementary Output States 1...

Страница 40: ...0 V or VIN VDD 5 A Vdd 3 3V unless specified otherwise Table 18 LVTTL input specifications Symbol Parameter Test condition MIN MAX Units VOH Output High Voltage VDD min IOH 2 mA 2 4 V VOL Output Low V...

Страница 41: ...cation Minimum voltage V Maximum voltage V LVDS 0 3 3 6 Opto isolated in 6 60 Opto isolated out 7 70 TTL 0 5 6 LVTTL 0 5 3 9 Note The maximum current that the Opto isolated out IOs can support is 150m...

Страница 42: ...or Device Links Model Host Links Device Links KY FGK 080 8 0 KY FGK 400 4 0 KY FGK 440 4 4 Table 23 Available Configurations Link Number KY FGK 080 KY FGK 400 KY FGK 440 0 Rx Rx Rx 1 Rx Rx Rx 2 Rx Rx...

Страница 43: ...level example design contains all the required project settings and an empty top level design for KOMODO CXP in Verilog and VHDL The top level design files can be found under fpga_top_level folder in...

Страница 44: ...he controller for the SODIMM bank is configured to use MT8KTF51264HZ 1G6E1 SODIMM module from Micron In addition to DDR3 memories the reference design includes PCI Express hard IP controller configure...

Страница 45: ...a documentation at http www altera com literature lit external memory interface jsp 9 1 2 PCI Express The PCI Express incorporates Altera hard IP configured in Gen2 x8 lanes mode The IP is connected t...

Страница 46: ...l the license follow the guidelines below 1 Save the license dat file received from KAYA Instruments on the hard drive 2 Open Quartus 3 For the web edition Using Tools license Setup license file choos...

Страница 47: ...board a messages from the IP should start appearing on the console Led Indicator Functionality DS1 Blinking in case PCI Express receives valid clock DS2 Lit when PCI Express IP is in L0 state DS3 Lit...

Страница 48: ...w steps Make sure Quartus II is installed on your PC Install KOMODO CXP board into the PC Connect the USB Blaster cable or USB Blaster II cable to the KOMODO CXP board and host PC Install the USB Blas...

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