XV-S62SL
1-40
X-Decoder
Address Buffer & Latches
Control Logic
A19~A0
/CE
/OE
/WE
16,777,216Bit
EEPROM
Cell Array
Y-Decoder
I/O Buffers & Data Latches
DQ15~DQ0
A19~A0
DQ15~DQ0
/CE
/OE
/WE
VDD
Vss
NC
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
To provide memory addresses. During sector erase A19~A11 address
lines will select the sector. During block erase A19~A15 address lines
will select the block.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are
in tri-state when /OE or /CE is high.
To activate the device when /CE is low.
To gate the data output buffers.
To control the write operations.
To provide 3-volt supply ( 2.7V-3.6V ).
Symbol
Function
Pin name
SST39VF160-7CEK (IC509) : 16M EEPROM
1. Pin layout
3. Pin function
2. Block diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
/WE
/RST
NC
NC
R/B
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
/BYTE
Vss
D15
D7
D14
D6
D13
D5
D12
D4
VDD
D11
D3
D10
D2
D9
D1
D8
D0
/OE
Vss
/CE
A0