JVC XV-N30BK[MK2], Руководство по обслуживанию

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(No.XA002)1-45
39-40 I/O DQ21~22 Multiplexed pins for data out put and input.
41 - VccQ Separated power from VCC, to improve DQ noise immunity. (+3.3V)
42 I/O DQ23 Multiplexed pins for data out put and input.
43 - Vcc Power for input buffers and logic circuit inside DRAM. (+3.3V)
44 - Vss Ground for input buffers and logic circuit inside DRAM.
45 I/O DQ24 Multiplexed pins for data out put and input.
46 I/O VssQ Separated power from VSS, to improve DQ noise immunity.
47-48 I/O DQ25~26 Multiplexed pins for data out put and input.
49 - VccQ Separated power from VCC, to im prove DQ noise immunity. (+3.3V)
50-51 I/O DQ27~28 Multiplexed pins for data out put and input.
52 I/O VssQ Separated power from VSS, to improve DQ noise immunity.
53-54 I/O DQ29~30 Multiplexed pins for data out put and input.
55 - VccQ Separated power from VCC, to improve DQ noise immunity. (+3.3V)
56 I/O DQ31 Multiplexed pins for data out put and input.
57 - NC No connection
58 - Vss Ground for input buffers and logic circuit inside DRAM.
59 I/O DQM3 The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle.
In write cycle sampling DQM high will block the write operation with zero latency.
60-66 - A3~A9 Multiplexed pins for row and column address. Row address: Ao-A10. Column address:A0-
A7.A10 is sampled during a recharge command to determine if all banks are to be recharged
or bank selected by BS0, BS1.
67 - CKE CKE controls the clock activation and deactivation. When CKE is low, Power Down rising edge
of clock.
68 I CLK System clock used to sample inputs on the rising edge of clock.
69-70 - NC No connection
71 I/O DQM1 The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle.
In write cycle, sampling DQM high will block the write operation with zero latency.
72 - Vss Ground for input buffers and logic circuit inside DRAM.
73 I/O NC No connection
74 I/O DQ8 Multiplexed pins for data out put and input.
75 I/O VccQ Separated power from VCC, to improve DQ noise immunity. (+3.3V)
76-77 I/O DQ9~10 Multiplexed pins for data out put and input.
78 I/O VssQ Separated power from VSS, to improve DQ noise immunity.
79-80 I/O DQ11~12 Multiplexed pins for data out put and input.
81 I/O VccQ Separated power from VCC, to improve DQ noise immunity. (+3.3V)
82-83 I/O DQ13~14 Multiplexed pins for data out put and input.
84 I/O VssQ Separated power from VSS, to improve DQ noise immunity.
85 I/O DQ15 Multiplexed pins for data out put and input.
86 - Vss Ground for input buffers and logic circuit inside DRAM.
Pin No. I/O Symbol Function