XL-SV320SL/SV305GD
XL-SV308BU
1-10
XL-SV320SL/305GD/308BU
ES3207 Pin description
Name
Number
I/O
Definition
VSS
1,2,25,26,29,30,31,
I
Ground.
72,75,77,91,100
VCC
3,4,5,16,32
I
Voltage supply 5V.
66,73,78,90
DSC-C
6
I
Clock for programming to access internal registers.
AUX[15:0]
40-38,36-34,20,18,
I/O
Auxiliary control pins.
14,67-70,11,9,7
DSC-D[7:0]
81,83,85,93,
I
Data for programming to access internal registers.
95,97,99,8
DSC-S
10
I
Strobe for programming to access internal registers.
DCLK/
12
O
Dual-purpose pin. DCLK is the mpeg decoder clock.
EXT-CLK
I
EXT-CLK is the external clock. EXT-CLK input during bypass PLL mode.
RST#
13
I
Video reset (active low).
MUTE
15
O
Audio mute.
MCLK
17
I
Audio master clock.
TWS/
I
Dual-purpose pin. TWS is the transmit audio frame sync.
SPLLOUT
19
O
SPLLOUT is the select PLL output.
TSD
21
I
Transmit audio data input.
TBCK
22
I
Transmit audio bit clock.
RWS/
O
Dual purpose pin. RWS is the receive audio frame sync.
SEL-PLL1
23
I
Pins SEL-PLL[1:0] select the PLL clock frequency for DCLK output.
SEL PLL1
SEL PLL0
DCLK
0
0
Bypass PLL (Input Mode)
0
1
27MHz (Output Mode)
1
0
32.4MHz (Output Mode)
1
1
40.5MHz (Output Mode)
RSTOUT#
24
O
Reset output (active low).
NC
27,28,65,76
No connect. Do not connect to these pins.
RSD/
33
O
Dual purpose pin. RSD is the receive audio data input.
SEL-PLL0
I
SEL-PLL0 is the select PLL. See the table for pin no. 23.
RBCK
37
O
Dual purpose pin. RBCK is the receive audio bit clock.
SER-IN
I
SER-IN is serial input DSC mode.
0=Parallel DSC mode.
1=Serial DSC mode.
VSSA
41,50,51,56,57,62,63 I
Analog ground.
VREFM
42
I
DAC and ADC minimum reference. Bypass to VCMR with 10µF in parallel with 0.1µF.
VREFP
43
I
DAC and ADC maximum reference. Bypass to VCMR with 10µF in parallel with 0.1µF.
VCCA
44,45,59,60
I
Analog VCC. 5V.
AOR
46
O
Right channel output.
AOL
47
O
Left channel output.
MIC2
48
I
Microphone input 2.
MIC1
49
I
Microphone input 1.
VREF
52
I
Internal resistor divider generates Common Mode Reference (CMR) voltage. Bypass to
analog ground with 0.1µF.
VCM
53
I
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25V.
Bypass to analog ground with 47µF electrolytic in parallel with 0.1µF.
RSET
54
I
Full scale DAC current adjustment.
COMP
55
I
Compensation pin.
CDAC
58
O
Modulated chrominance output.
YDAC
61
O
Y luminance data bus for screen video port.
VDAC
64
O
Composite video output.
XOUT
71
O
Crystal output.
XIN
74
I
27MHz crystal input.
PCLK
79
I/O
13.5MHz pixel clock.
PCLK2X
80
I/O
27MHz (2 times pixel clock).
HSYNC#
82
I/O
Horizontal sync (active low).
VSYNC#
84
I/O
Vertical sync (active low).
YUV[7:0]
86-89,92,94,96,98
O
YUV luminance and chrominance data bus for screen video port.
Содержание XL-SV302SL
Страница 7: ...XL SV320SL 305GD 308BU 1 7 Pin configuration U1 ES3210 Block diagram Pin configuration ...
Страница 9: ...XL SV320SL 305GD 308BU 1 9 U4 ES3207 Block diagram Pin configuration ...
Страница 13: ...XL SV320SL 305GD 308BU 1 13 U5 CXD3068Q CD DSP Block diagram ...
Страница 29: ...XL SV320SL SV305GD XL SV308BU 2 2 XL SV320SL 305GD 308BU Wiring diagram ...
Страница 30: ...XL SV320SL 305GD 308BU 2 3 Block diagram ...
Страница 31: ...XL SV302SL 305GD 308BU Schematic Diagrams MIC AMP Power Key VFD Circuit 2 4 ...
Страница 32: ...MPEG Circuit XL SV302SL 305GD 308BU 2 5 ...
Страница 33: ...Servo Circuit XL SV302SL 305GD 308BU 2 6 ...
Страница 34: ...Output Circuit XL SV302SL 305GD 308BU 2 7 ...
Страница 35: ...D A Circuit XL SV302SL 305GD 308BU 2 8 ...
Страница 36: ...Memory Circuit XL SV302SL 305GD 308BU 2 9 ...
Страница 38: ...MPEG Servo and Output PCB XL SV302SL 305GD 308BU Top View 2 11 ...
Страница 39: ...XL SV302SL 305GD 308BU MIC AMP Board 2 12 ...
Страница 40: ...XL SV302SL 305GD 308BU Key and FLD Display Board 2 13 ...
