JVC UX-A10DVD, Руководство по обслуживанию

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1-87
UX-A10DVD
Pin No.
171
172
173
174
175
176
177
178
179
180
181
182~184
185~187
188
189
190
191
192
193~196
197
198
199~203
204
205
206~207
208
Symbol
VDACK
VREQUEST
VSTROBE
ERROR
VDD_3.3
RESERVED
VDD_3.3
VSS
NC
RESERVED
NC
HADDR0~2
RESERVED
VSS
VDD_2.5
RESERVED
VSS
VDD_3.3
RESERVED
HDATA7
VSS
HDATA6~2
VDD_3.3
VSS
HDATA1,0
CS
I/O
I
O
I
I
Power
I
Power
Ground
O
I
O
I
I
Ground
Power
I
Ground
Power
I
I/O
Ground
I/O
Power
Ground
I/O
I
Function
In synchronous mode,bitstream data acknowledge.Asserted when DVD data is
valid.Polarity is programmable.
Bitstream request.Decoder asserts VREQUEST to indicate that the bitstream
input buffer has available space.Polarity is programmable.
Bitstream strobe.Programmable dual mode pulse.Asynchronous and
synchronous.In Asynchronous mode,an external source pulses VSTROBE to
indicate data is ready for transfer.In synchronous mode,VSTROBE clocks data.
Error in input data.If ERROR signal is not available from the DSP it must be
grounded.
3.3-V supply voltage for I/O signals.
Tie to VSS or VDD_3.3 as specified in Table 1.
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals
No connect.
Tie to VSS or VDD_3.3 as specified in Table 1.
No connect.
Host address bus.3-bit address bus selects one of eight host interface registers.
Tie to VSS or VDD_3.3 as specified in Table 1.
Ground for core logic and I/O signals
2.5-V supply voltage for core logic
Tie to VSS or VDD_3.3 as specified in Table 1.
Ground for core logic and I/O signals
3.3-V supply voltage for I/O signals.
Tie to VSS or VDD_3.3 as specified in Table 1.
HDATA(7~0) is the 8-bit bi-directional host data bus through which the host
writes data to the decoder Code FIFO.MSB of the 32-bit word is written first.
The host also reads and writes the decoder internal registers and local
SDRAM/ROM via HDATA(7~0).
Ground for core logic and I/O signals
HDATA(7~0) is the 8-bit bi-directional host data bus through which the host
writes data to the decoder Code FIFO.MSB of the 32-bit word is written first.
The host also reads and writes the decoder internal registers and local
SDRAM/ROM via HDATA(7~0).
3.3-V supply voltage for I/O signals.
Ground for core logic and I/O signals
HDATA(7~0) is the 8-bit bi-directional host data bus through which the host
writes data to the decoder Code FIFO.MSB of the 32-bit word is written first.
The host also reads and writes the decoder internal registers and local
SDRAM/ROM via HDATA(7~0).
Host chip select Host asserts CS to select the decoder for a read or write
operation.The falling edge of this signal triggers the read or write operation.
2.Pin function 4/4