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UX-A10DVD
K4S641632F-TC75
3.Pin function
1
2
3
4,5
6
7,8
9
10,11
12
13
14
15
16
17
18
19
20,21
22~26
27,28
29~35
36
37
38
39
40
41
42
43
44,45
46
47,48
49
50,51
52
53
54
VDD
DQ0
VDDQ
DQ1,DQ2
VSSQ
DQ3,DQ4
VDDQ
DQ5,DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0,BA1
A10/AP,
A0~A3
VDD,VSS
A4~A9,
A11
N.C
CKE
CLK
UDQM
N.C/RFU
VSS
DQ8
VDDQ
DQ9,DQ10
VSSQ
DQ11,DQ12
VDDQ
DQ13,DQ14
VSSQ
DQ15
VSS
Power and ground for the input buffers and the core logic.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Power and ground for the input buffers and the core logic.
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Enables wnite operation and row precharge.
Latches data in starting from CAS,WE active.
Latches column addresses on the positlve going edge of the CLK with CAS low.
Enables column access.
Latches row addresses on the positlve going edge of the CLK with RAS low.
Enables row access & precharge.
Disables or enables device oparation by masking or enabling all inputs except
CLK,CKE and L(U)DQM
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Row/column addresses are multiplexed on the same plns.
Row address : RA0~RA11, Column address : CA0~CA7
Power and ground for the input buffers and the core logic.
Row/column addresses are multiplexed on the same plns.
Row address : RA0~RA11, Column address : CA0~CA7
This pin is recommended to be left No Connection on the device.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Dlsable input buffers for power down in standby.
Active on the positlve going edge to sample all inputs.
Makes data output Hi-Z, tsHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
This pin is recommended to be left No Connection on the device.
Power and ground for the input buffers and the core logic.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Isolated power supply and ground for the output buffers to provide improved noise
Immunity.
Data inputs/outputs are muitiplexed on the same plns.
Power and ground for the input buffers and the core logic.
Function
Pin No.
Symbol
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