KD-SH707
1-51
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
1. Pin layout
W24L010AJ-12 (IC653) : SRAM
DECODER
CORE
ARRAY
CONTROL
DATA I/O
V
DD
Vss
CS2
CS1
OE
WE
A0
A16
I/O1
I/O8
2. Block diaglam
3. Pin function
SYMBOL
A0 - A16
I/O1 - I/O8
CS1, CS2
WE
OE
V
DD
Vss
NC
DESCRIPTION
Address Input
Data Input/Output
Chip Select Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
A
B
4
8
7
6
5
V-
V+
B OUT
B -IN
B +IN
NJM4580M-X (IC371,IC471) : EEPROM
1.Terminal layout & Block diagram
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9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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