JVC InteriArt LT-26A61BU, Руководство по обслуживанию

Страница: 9 / 174

(No.YA369)1-9
2.5.2 MAIN CPU PIN FUNCTION [U302 : MAIN PWB]
Pin Pin name I/O Function Pin Pin name I/O Function
1 D1 I/O Program ROM data for CPU 51 NC2 - Not used
2 D4 I/O Program ROM data for CPU 52 XTAL2 O 6MHz for system clock
3 D2 I/O Program ROM data for CPU 53 XTAL1 I 6MHz for system clock
4 D3 I/O Program ROM data for CPU 54 NC3 - Not used
5 XROM O This pin must be pulled low to access external ROM. 55 VSSA - GND
6 VDD 2.5 I 2.5V 56 VDDA 2.5 I 2.5V
7 VSS - GND 57 R O R for teletext
8 VDD 3.5 I 3.5V 58 G O G for teletext
9 P0.0 I/O Address/Data for scaler IC 59 B O B for teletext
10 P0.1 I/O Address/Data for scaler IC 60 BLANK/COR O Ys for Teletext
11 P0.2 I/O Address/Data for scaler IC 61 NC4 - Not used
12 P0.3 I/O Address/Data for scaler IC 62 P1.7 O Reset for Scaler IC [H=Reset]
13 P0.4 - Not used 63 NC5 - Not used
14 P0.5 O Address latch Enable 64 WR O Write for memory
15 P0.6 - Not used 65 RD O Read for memory
16 P0.7 - Not used 66 NC6 Not used
17 ENE - Not used 67 A19 O Program ROM address for CPU
18 STOP - Not used 68 A18 O Program ROM address for CPU
19 OCF - Not used 69 A16 O Program ROM address for CPU
20 EXTIF - Not used 70 A17 O Program ROM address for CPU
21 CVBS I Video for teletext 71 A15 O Program ROM address for CPU
22 VDDA 2.5 I 2.5V 72 FL_PGM - Test purpose
23 VSSA - GND 73 VDD 2.5 I 2.5V
24 P2.0 I Scart2 ID [H=Detect] 74 VSS - GND
25 P2.1 I key scan data 1 75 VDD 3.3 I 3.3V
26 P2.2 I key scan data 2 76 A14 O Program ROM address for CPU
27 P2.3 I Scaet1 ID [H=Detect] 77 A12 O Program ROM address for CPU
28 NC1 - Not used 78 A13 O Program ROM address for CPU
29 HS/SSC I Horizontal sync 79 A7 O Program ROM address for CPU
30 VS I Vertical sync 80 FL_RST - Test purpose
31 P3.0 O Data Read for Scaler IC 81 A8 O Program ROM address for CPU
32 P3.1 O Comunication for adjustment [H=TXD] 82 A6 O Program ROM address for CPU
33 P3.2 I TV-Link in 83 A9 O Program ROM address for CPU
34 P3.3 I Remote control 84 A5 O Program ROM address for CPU
35 P3.4 I/O I2C bus Data(for EEPROM) 85 A11 O Program ROM address for CPU
36 P3.5 O I2C bus Clock(for EEPROM) 86 A4 O Program ROM address for CPU
37 P3.6 O Data Write for Scaler IC 87 ALE O Address Latch Enable
38 P3.7 I Comunication for adjustment [H=RXD] 88 PSEN O Program Store Enable
39 VSS - GND 89 A3 O Program ROM address for CPU
40 VDD 3.3 I 3.3V 90 A10 O Program ROM address for CPU
41 P1.0 O RGB Select [L=SCART1, H=SCART2] 91 VSS - GND
42 P1.1 I Headphone Ident [L=Detect] 92 VDD 3.3 I 3.3V
43 P1.2 I/O I2C bus Data(for inter IC) 93 A2 O Program ROM address for CPU
44 P1.3 O I2C bus Clock(for inter IC) 94 A1 O Program ROM address for CPU
45 P1.4 O Reset for inter IC [L=Reset] 95 FL_CE - Test purpose
46 P1.5 I PC Detect [L=Detect] 96 D7 I/O Program ROM data for CPU
47 P1.6 O Memory Pack I2C S/W [L=Detect] 97 A0 O Program ROM address for CPU
48 P4.2 O Main power control [L=ON, H=OFF] 98 D6 I/O Program ROM data for CPU
49 P4.3 O TV-Link out 99 D0 I/O Program ROM data for CPU
50 RST O Reset [L=Reset] 100 D5 I/O Program ROM data for CPU