4-19
D
C
B
A
4
5
3
2
1
FIL
TO
TO TERMINAL
3D DIGITAL
0 3 MAIN(S-SUB)
YFBC
2D DIGITAL
COMP
TO
YMUTE
CMUT
ATT
ATT
CL2
CL2
POSLPF1
POSLPF2
+1dB
BF
BF
+6
CK
NC
VCA
PRE
LPF2
PRE
LPF1
BG
CR ADJ
ATT
GCL
SSEP
LIM2
DC
LIM1
REGEN
REC
PB SW11
DIG OSD
DIG OSD
SW10
CH1-C
CH2-C
SW17
SW1
PB
REC
SW19
REC
PB
SW2
DIG
DIG
SW3
PB*+1dB
PB*0dB
SW4
REC+
SW5
CONV
CONV
DIG
DIG
SW8
CONV
CONV
SW7
OSD
OSD
SW14
SW13
OSD
OSD
FIL
DIG
PB
REC
SW12
SW9
SW16
O
OSD
SW15
DIG
OSD
SW6
EXT IN
REC
∗
EXT IN
VCC3
YC MUTE
ACC:ON
D13
D1*D14*D15
VIDEO
VCC1
PB-Y
VHS[H]
GND3
SP[H]
PB[H]
PAL[H]
DATA
CLK
IC501
CN501
C539
CHARA_DATA
SLOW_PULSE
B502
TRICK[H]
D.FF
L504
C522
V.REF
VP_CTL
C532
L506
GND
C_FROM_DIGI
Y_FROM_DIGI
D502
C523
C529
C524
C520
C527
C528
I2C_DATA_A/V
I2C_CLK_A/V
C525
CTL5
C_IN_CH2
GND
C_IN_CH1
V/Y_TO_DIGI
C521
GND
L503
D501
C530
C502
C501
SW5V
C_TO_DIGI
GND
Fsc
B503
R510
GND
Y_OUT
C_OUT
P.MUTE[L]
V_FROM_OSD
GND
I2C_DATA_A/V
I2C_CLK_A/V
0.01
4.7
0.01
0.01
10
2.2
0.1
0.01
0.01
0.01
0.01
47
4.7M
JCP8058
Fsc
GND
GND
SLOW_PULSE
OPEN
TRICK[H]
D.FF
V.REF
VP_CTL
I2C_DATA_A/V
I2C_CLK_A/V
CTL5
C_FROM_DIGI
Y_FROM_DIGI
EE[L]
V/Y_TO_DIGI
SW5V[2]
C_TO_DIGI
SHOR
T
/50
OPEN
OPEN
OPEN
/25
/50
OPEN
OPEN
OPEN
/6.3
#
#
#
NC
TO SYSCON
(N/US PWB)
MODEL
US, UM, UC
2D
JP
3D
L504
C530
CN501
#DIFFERENCE TABLE 1
#DIFFERENCE TABLE 2
(N/JP PWB)
: USED
: NOT USED
4.9 MAIN (S-SUB) SCHEMATIC DIAGRAM