A
1
2
3
4
5
B
C
D
E
F
G
DIGITAL(1394PHY)
0 2
IC1801
PHY_LPS
CN1801
TO JACK
CN4104
R1818
L1801
L1802
C1804
RA1801
C1805
C1803
C1806
PHY_CTL[0]
X1801
RA1802
B1801
B1802
D3.3V
TO MEDIA PROCESSOR
R1820
PHY_CNA
K1801
C1813
C1810
R1801
PHY_DATA[0-7]
PHY_CTL[1]
PHY_CLK
PHY_LINK_ON
PHY_RESET[L]
R1802
R1819
PHY_LREQ
C1814
GND
R1823
T1801
T1801
T1801
T1801
T1801
T1801
T1801
T1801
R1805
R1810
R1806
R1812
R1808
R1807
R1809
C1801
R1821
R1811
C1808
R1822
C1809
C1807
C1811
C1812
R1813
R1814
R1815
R1816
R1817
C1802
R1803
R1804
LREQ
SYSCLK
CNA
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PD
LPS
NC
AGND
TPB0-
TPB0+
TPA0-
AGND
R0
TPA0+
TPBIAS0
R1
AVDD
NC
NC
NC
AGND
NC
NC
TSB41AB2PAP
#
QGB2027L1-10X
#
_0.5%
#
#
OPEN
#
#
/6.3
#
/6.3
#
NAX0551-001X
NAX0666-001X
#
OPEN
#
#
SHORT
#
OPEN
OPEN
#
#
_0.5%
#
OPEN
##
NQR0444-001X
#
NQR0444-001X
NQR0444-001X
NQR0444-001X
NQR0444-001X
NQR0444-001X
NQR0444-001X
NQR0444-001X
#
DGND
DGND
C/LKON
PC0
PC1
PC2
ISO
CPS
DVDD
DVDD
TESTM
BRIDGE
TEST0
AVDD
AVDD
AGND
DGND
DGND
DVDD
DVDD
XO
XI
PLLGND
PLLGND
PLLVDD
NC
NC
RESET
AVDD
AVDD
AGND
AGND
#
OPEN
#
##
#
#
#
#
OPEN
#
#
#
#
#
#
#
#
#
#
#
#
5.6k
10
µ
0.1
10k
0.1
10
10
10k
10k
0
Ω
0
Ω
750
0
Ω
0
Ω
390k
0
Ω
10k
10k
10k
1
1k
12p
0
Ω
12p
0.1
0.1
0.1
56
56
56
56
5.1k
270p
10k
10k
TPB0+
TPA0-
TPA+
TPA-
TPB+
TPBIAS0
TPB-
PHY_DATA[0]
PHY_DATA[1]
PHY_DATA[3]
PHY_DATA[4]
PHY_DATA[5]
TPB0-
GND
PHY_DATA[0-7]
TPA0+
PHY_DATA[7]
D3.3V
PHY_DATA[6]
PHY_DATA[2]
1801_X0
1801_XI
p30122001a_rev1
DIGITAL(1394PHY) SCHEMATIC DIAGRAM
2-15
2-16
Содержание DR-MV1SUS
Страница 23: ... No YD006 1 23 ...