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Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Phoenix – AwardBIOS CMOS Setup Utility
VDIMM SELECT
Item Help
CPU Clock At Next Boot 200
PCIE Reference clock 100
SB Reference clock 100
Spread Spectrum Enabled
AMD K8 Cool&Quiet Control Disabled
VDIMM Select 1.95v
NB Voltage setting 1.15v
Memory Clock Mode Auto
DRAM CLOCK at Next Boot DDR533
Menu Level >
VDIMM Select
1.85v [ ]
1.90v [ ]
………
2.00v [ ]
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Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
CPU/HT Reference Clock
Immediately press F12 key to load defaults after pressing the
power button or reset button.
CPU
Vcore
This item allows you select the CPU Vcore Voltage xx% more than the standard value, by
this function for the precise over-clocking for extra demanding of performance.
NB Voltage
This item allows you to select value of Voltage for North Bridge Chipset.
IH Flow-Control Mode:
Isochronous (ISOC) Flow Control Mode enable will make the HT Link communication have
the complex ordering rules for Isochronous source to make sure it can get service from the
system with deterministic worst-case latency. However, the latency time cost of ISOC flow
control mode is an important consideration. Normal flow control mode will be a simpler
solution for most system.
HT Link Tristate:
Disabled mode will make the link transmitter is driven but in and under fined state during the
disconnect sequence. And the PHY (transmitter) is placed in LS0. LS0 state keeps all lanes
active to maintain DLL and phase recovery lock.
Enabled mode will make the link transmitter is placed into high impedance states during the
disconnect sequence. And the PHY (transmitter) is placed in LS1, LS2 or LS3. LS1, LS2 and
LS3 are each states that shut down parts of the PHY to save power.
LS1 state: CLK running, CAD/CTL sending TxIdle.
LS2 state: CLK/CAD/CTL sending TxIdle.
LS3 state: CLK/CAD/CTL sending either HiZ or TxGndTrm.
UnitID Clumping:
Originally, a single UnitID only allow 32 outstanding nonposted transactions within the chain.
If a device uses more than one UnitID to achieve greater concurrency, the transactions in
different UnitIDs are not required to be ordered together.
