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3-6-2 LDT & PCI Timing Settings
Phoenix – AwardBIOS CMOS Setup Utility
LDT & PCI Timing Settings
Item Help
Upstream LDT Bus Width 16 bit
Downstream LDT Bus Width 16 bit
LDT Bus Frequency Auto
PCI1 Master 0 WS Write Enabled
PCI2 Master 0 WS Write Enabled
PCI1 Post Write Enabled
PCI2 Post Write Enabled
PCI Delay Transaction Disabled
VLink Mode Selection Mode 4
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
3-7 Integrated Peripherals
Phoenix – AwardBIOS CMOS Setup Utility
Integrated Peripherals
Item Help
> OnChip IDE Function Press Enter
> OnChip Device Function Press Enter
> Onboard Super IO Function Press Enter
Init Display First PCI Slot
Menu Level >
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
OnChip IDE Function
Please refer to section 3-7-1
OnChip Device Function
Please refer to section 3-7-2
Onboard Super IO Function
Please refer to section 3-7-3
Init Display First
This item allows you to decide to activate whether PCI Slot or AGP VGA first. The settings
are: PCI Slot, AGP Slot.