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operations with bilinear interpolation in both horizontal and
vertical directions. The linear scaling permits zoom in/out to
any size without any restrictions. In addition, the on-chip
hardware Color Space Conversion (CSC) accelerates
conversion for 16 bit YUV pixels into linear true color 32 bit
RGB pixels on the fly. The additional X and Y minifiers are
capable of shrinking the video images to any linear fractions,
which saves bus bandwidths and memory space. The YUV
planar of the Video 107AGP 3D & TV supports a YUV 420
format that can remove redundant video stream decoding
procedures. The load of the CPU is reduced while performing
SW MPEG or SW video conferencing. The color and
luminance control provided by the Video 107AGP 3D & TV
offers color compensations to prevent color distortion for
display devices such as a CRT or TV with Gamma correction
and hue adjustment control.
The Video Conferencing feature allows remote and local video
images to be displayed simultaneously on the same screen.
2.14 Video Capture and DVD
The Video 107AGP 3D & TV has an 8-bit Video Module
Interface (VMI) compatible interface, allowing it to be directly
connected to many MPEG and video decoders such as the C-
Cube CL450/480, SGS 3400/3500, Philips 7110/1 and
Brooktree BT819/817/827/829.
The Video 107AGP 3D & TV, integrated with a DVD video
hardware block for motion compensation, gives existing PCs
the ability to play DVD video in MPEG-2 format at high
bandwidths with very good video quality.
A new industry standard is being set for transmission of non-
video data over a TV broadcast signal during vertical blanking
dead time. This technology is referred to as Intercast. The
Video 107AGP 3D & TV has the ability to take the entire video
stream over the video port, sending the visible video stream to
the display memory for display in a window, stripping the VBI
data from the stream, and then sending this data to the CPU
for processing using PCI Bus Mastering.
2.15 Versatile Frame Buffer Interface
The Video 107AGP 3D & TV features a versatile frame buffer
interface, providing SDRAM/SGRAM interface flexibility to
meet the demand of high-end and mid-end notebook designs.
Optimized performance can be achieved with the single cycle
memory bus interface using programmable DRAM timing. The
display queue has been increased to reduce the frequency of
the memory bus requests, optimizing the memory bus
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