IWILL P55XPLUS, Руководство пользователя

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is for CPU Core (Vcore), the other is for CPU input/output single (Vio). The JP2 pin 1 is
connected to the CPU Vcore and pin 2 is connected to the CPU Vio.
2.4 L2 Cache Memory
The second level L2 cache memory supports pipelined burst SRAM, it will has much
higher performance compared with the traditional asynchronous SRAM. This
motherboard uses the new pipelined burst cache technology with 512K size and the
memory cacheable size from 64MB to 512MB (Extra Tag RAM is needed) .
2.5 D-RAM Configuration
This motherboard provides two DIMMs and four SIMMs memory sockets. At least one
piece 72 pin SIMM (Single In-line Memory Module) or one piece 168 pin DIMM (Dual
In-line Memory Module)must be inserted in this P55XPlus Ultra DMA 33 motherboard.
1.
Two DIMM (DIMM 1, DIMM 2) sockets—support 3.3V Unbuffered
Synchronous DRAM (SDRAM). Each DIMM memory size can be
8/16/32/64/128/256 MByte. The maximum memory is 512 MByte that the
ALI Aladdin 4+ Chipset maximum can support.
2.
Four SIMM sockets (Bank 0, Bank 1)—support Fast Page and EDO
DRAM. These four SIMMs sockets are devided into two groups by each
two SIMM sockets. Each two SIMM in the same group must be the same
memory size and type, the Fast Page and EDO DRAM can not be mixed in
the same group.
3.
When second tag ram is installed for memory cacheable size to reach
512MB, the SIMM 1 and SIMM 2 can not be installed.
IR
SIMM1
SIMM2
SIMM3
SIMM4
DIMM1
DIMM2
Install the SIMM